stm32f10x_tim.txt

stm32 ucos 精简移殖版本 不需作任何修改直接便可运行。包含串口 定时器

;;;309      TIMx->CR2 = tmpcr2;
00015e  8083              STRH     r3,[r0,#4]
;;;310      
;;;311      /* Write to TIMx CCMR1 */
;;;312      TIMx->CCMR1 = tmpccmrx;
000160  8304              STRH     r4,[r0,#0x18]
;;;313      
;;;314      /* Write to TIMx CCER */
;;;315      TIMx->CCER = tmpccer;
000162  8402              STRH     r2,[r0,#0x20]
;;;316    }
000164  bd30              POP      {r4,r5,pc}
;;;317    
                          ENDP

                  TIM_OC2Init PROC
;;;330    void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
;;;331    {
000166  b530              PUSH     {r4,r5,lr}
;;;332      u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
;;;333       
;;;334      /* Check the parameters */
;;;335      assert_param(IS_TIM_123458_PERIPH(TIMx)); 
;;;336      assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;337      assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;338      assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
;;;339    
;;;340      /* Disable the Channel 2: Reset the CC2E Bit */
;;;341      TIMx->CCER &= CCER_CC2E_Reset;
000168  8c02              LDRH     r2,[r0,#0x20]
00016a  f022f022          BIC      r2,r2,#0x10
00016e  8402              STRH     r2,[r0,#0x20]
;;;342      
;;;343      /* Get the TIMx CCER register value */  
;;;344      tmpccer = TIMx->CCER;
000170  8c02              LDRH     r2,[r0,#0x20]
;;;345    
;;;346      /* Get the TIMx CR2 register value */
;;;347      tmpcr2 =  TIMx->CR2;
000172  8883              LDRH     r3,[r0,#4]
;;;348      
;;;349      /* Get the TIMx CCMR1 register value */
;;;350      tmpccmrx = TIMx->CCMR1;
000174  8b04              LDRH     r4,[r0,#0x18]
;;;351        
;;;352      /* Reset the Output Compare Mode Bits */
;;;353      tmpccmrx &= CCMR_OC24M_Mask;
000176  f424f424          BIC      r5,r4,#0x7000
;;;354      
;;;355      /* Select the Output Compare Mode */
;;;356      tmpccmrx |= (u16)(TIM_OCInitStruct->TIM_OCMode << 8);
00017a  880c              LDRH     r4,[r1,#0]
00017c  0624              LSLS     r4,r4,#24
00017e  ea45ea45          ORR      r4,r5,r4,LSR #16
;;;357      
;;;358      /* Reset the Output Polarity level */
;;;359      tmpccer &= CCER_CC2P_Reset;
000182  f022f022          BIC      r2,r2,#0x20
;;;360    
;;;361      /* Set the Output Compare Polarity */
;;;362      tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 4);
000186  890d              LDRH     r5,[r1,#8]
000188  052d              LSLS     r5,r5,#20
00018a  ea42ea42          ORR      r5,r2,r5,LSR #16
;;;363      
;;;364      /* Set the Output State */
;;;365      tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 4);
00018e  884a              LDRH     r2,[r1,#2]
000190  0512              LSLS     r2,r2,#20
000192  ea45ea45          ORR      r2,r5,r2,LSR #16
;;;366      
;;;367      /* Set the Capture Compare Register value */
;;;368      TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
000196  88cd              LDRH     r5,[r1,#6]
000198  8705              STRH     r5,[r0,#0x38]
;;;369      
;;;370      if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
00019a  4d97              LDR      r5,|L1.1016|
00019c  42a8              CMP      r0,r5
00019e  d002              BEQ      |L1.422|
0001a0  4d96              LDR      r5,|L1.1020|
0001a2  42a8              CMP      r0,r5
0001a4  d117              BNE      |L1.470|
                  |L1.422|
;;;371      {
;;;372        assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
;;;373        assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
;;;374        assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
;;;375        assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;376        
;;;377        /* Reset the Output N Polarity level */
;;;378        tmpccer &= CCER_CC2NP_Reset;
0001a6  f022f022          BIC      r2,r2,#0x80
;;;379    
;;;380        /* Set the Output N Polarity */
;;;381        tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
0001aa  894d              LDRH     r5,[r1,#0xa]
0001ac  052d              LSLS     r5,r5,#20
0001ae  ea42ea42          ORR      r5,r2,r5,LSR #16
;;;382    
;;;383        /* Reset the Output N State */
;;;384        tmpccer &= CCER_CC2NE_Reset;
0001b2  f025f025          BIC      r5,r5,#0x40
;;;385        
;;;386        /* Set the Output N State */
;;;387        tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputNState << 4);
0001b6  888a              LDRH     r2,[r1,#4]
0001b8  0512              LSLS     r2,r2,#20
0001ba  ea45ea45          ORR      r2,r5,r2,LSR #16
;;;388    
;;;389        /* Reset the Ouput Compare and Output Compare N IDLE State */
;;;390        tmpcr2 &= CR2_OIS2_Reset;
0001be  f423f423          BIC      r3,r3,#0x8400
;;;391        tmpcr2 &= CR2_OIS2N_Reset;
0001c2  f423f423          BIC      r3,r3,#0x8800
;;;392    
;;;393        /* Set the Output Idle state */
;;;394        tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 2);
0001c6  898d              LDRH     r5,[r1,#0xc]
0001c8  04ad              LSLS     r5,r5,#18
0001ca  ea43ea43          ORR      r5,r3,r5,LSR #16
;;;395    
;;;396        /* Set the Output N Idle state */
;;;397        tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
0001ce  89c9              LDRH     r1,[r1,#0xe]
0001d0  0489              LSLS     r1,r1,#18
0001d2  ea45ea45          ORR      r3,r5,r1,LSR #16
                  |L1.470|
;;;398      }
;;;399    
;;;400      /* Write to TIMx CR2 */
;;;401      TIMx->CR2 = tmpcr2;
0001d6  8083              STRH     r3,[r0,#4]
;;;402      
;;;403      /* Write to TIMx CCMR1 */
;;;404      TIMx->CCMR1 = tmpccmrx;
0001d8  8304              STRH     r4,[r0,#0x18]
;;;405      
;;;406      /* Write to TIMx CCER */
;;;407      TIMx->CCER = tmpccer;
0001da  8402              STRH     r2,[r0,#0x20]
;;;408    }
0001dc  bd30              POP      {r4,r5,pc}
;;;409    
                          ENDP

                  TIM_OC3Init PROC
;;;422    void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
;;;423    {
0001de  b530              PUSH     {r4,r5,lr}
;;;424      u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
;;;425       
;;;426      /* Check the parameters */
;;;427      assert_param(IS_TIM_123458_PERIPH(TIMx)); 
;;;428      assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;429      assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;430      assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
;;;431    
;;;432      /* Disable the Channel 2: Reset the CC2E Bit */
;;;433      TIMx->CCER &= CCER_CC3E_Reset;
0001e0  8c02              LDRH     r2,[r0,#0x20]
0001e2  f422f422          BIC      r2,r2,#0x100
0001e6  8402              STRH     r2,[r0,#0x20]
;;;434      
;;;435      /* Get the TIMx CCER register value */
;;;436      tmpccer = TIMx->CCER;
0001e8  8c02              LDRH     r2,[r0,#0x20]
;;;437    
;;;438      /* Get the TIMx CR2 register value */
;;;439      tmpcr2 =  TIMx->CR2;
0001ea  8883              LDRH     r3,[r0,#4]
;;;440      
;;;441      /* Get the TIMx CCMR2 register value */
;;;442      tmpccmrx = TIMx->CCMR2;
0001ec  8b84              LDRH     r4,[r0,#0x1c]
;;;443        
;;;444      /* Reset the Output Compare Mode Bits */
;;;445      tmpccmrx &= CCMR_OC13M_Mask;
0001ee  f024f024          BIC      r5,r4,#0x70
;;;446      
;;;447      /* Select the Output Compare Mode */
;;;448      tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
0001f2  880c              LDRH     r4,[r1,#0]
0001f4  432c              ORRS     r4,r4,r5
;;;449      
;;;450      /* Reset the Output Polarity level */
;;;451      tmpccer &= CCER_CC3P_Reset;
0001f6  f422f422          BIC      r2,r2,#0x200
;;;452    
;;;453      /* Set the Output Compare Polarity */
;;;454      tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 8);
0001fa  890d              LDRH     r5,[r1,#8]
0001fc  062d              LSLS     r5,r5,#24
0001fe  ea42ea42          ORR      r5,r2,r5,LSR #16
;;;455      
;;;456      /* Set the Output State */
;;;457      tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 8);
000202  884a              LDRH     r2,[r1,#2]
000204  0612              LSLS     r2,r2,#24
000206  ea45ea45          ORR      r2,r5,r2,LSR #16
;;;458      
;;;459      /* Set the Capture Compare Register value */
;;;460      TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
00020a  88cd              LDRH     r5,[r1,#6]
00020c  8785              STRH     r5,[r0,#0x3c]
;;;461      
;;;462      if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
00020e  4d7a              LDR      r5,|L1.1016|
000210  42a8              CMP      r0,r5
000212  d002              BEQ      |L1.538|
000214  4d79              LDR      r5,|L1.1020|
000216  42a8              CMP      r0,r5
000218  d117              BNE      |L1.586|
                  |L1.538|
;;;463      {
;;;464        assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
;;;465        assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
;;;466        assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
;;;467        assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;468        
;;;469        /* Reset the Output N Polarity level */
;;;470        tmpccer &= CCER_CC3NP_Reset;
00021a  f422f422          BIC      r2,r2,#0x800
;;;471    
;;;472        /* Set the Output N Polarity */
;;;473        tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
00021e  894d              LDRH     r5,[r1,#0xa]
000220  062d              LSLS     r5,r5,#24
000222  ea42ea42          ORR      r5,r2,r5,LSR #16
;;;474    
;;;475        /* Reset the Output N State */
;;;476        tmpccer &= CCER_CC3NE_Reset;
000226  f425f425          BIC      r5,r5,#0x400
;;;477        
;;;478        /* Set the Output N State */
;;;479        tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputNState << 8);
00022a  888a              LDRH     r2,[r1,#4]
00022c  0612              LSLS     r2,r2,#24
00022e  ea45ea45          ORR      r2,r5,r2,LSR #16
;;;480    
;;;481        /* Reset the Ouput Compare and Output Compare N IDLE State */
;;;482        tmpcr2 &= CR2_OIS3_Reset;
000232  f423f423          BIC      r3,r3,#0x9000
;;;483        tmpcr2 &= CR2_OIS3N_Reset;
000236  f423f423          BIC      r3,r3,#0xa000
;;;484    
;;;485        /* Set the Output Idle state */
;;;486        tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 4);
00023a  898d              LDRH     r5,[r1,#0xc]
00023c  052d              LSLS     r5,r5,#20
00023e  ea43ea43          ORR      r5,r3,r5,LSR #16
;;;487    
;;;488        /* Set the Output N Idle state */
;;;489        tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
000242  89c9              LDRH     r1,[r1,#0xe]
000244  0509              LSLS     r1,r1,#20
000246  ea45ea45          ORR      r3,r5,r1,LSR #16
                  |L1.586|
;;;490      }
;;;491    
;;;492      /* Write to TIMx CR2 */
;;;493      TIMx->CR2 = tmpcr2;
00024a  8083              STRH     r3,[r0,#4]
;;;494      
;;;495      /* Write to TIMx CCMR2 */
;;;496      TIMx->CCMR2 = tmpccmrx;
00024c  8384              STRH     r4,[r0,#0x1c]
;;;497      
;;;498      /* Write to TIMx CCER */
;;;499      TIMx->CCER = tmpccer;
00024e  8402              STRH     r2,[r0,#0x20]
;;;500    }
000250  bd30              POP      {r4,r5,pc}
;;;501    
                          ENDP

                  TIM_OC4Init PROC
;;;514    void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
;;;515    {
000252  b530              PUSH     {r4,r5,lr}
;;;516      u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
;;;517       
;;;518      /* Check the parameters */
;;;519      assert_param(IS_TIM_123458_PERIPH(TIMx)); 
;;;520      assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;521      assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;522      assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
;;;523    
;;;524      /* Disable the Channel 2: Reset the CC4E Bit */
;;;525      TIMx->CCER &= CCER_CC4E_Reset;
000254  8c02              LDRH     r2,[r0,#0x20]
000256  f422f422          BIC      r2,r2,#0x1000
00025a  8402              STRH     r2,[r0,#0x20]
;;;526      
;;;527      /* Get the TIMx CCER register value */
;;;528      tmpccer = TIMx->CCER;
00025c  8c04              LDRH     r4,[r0,#0x20]
;;;529    
;;;530      /* Get the TIMx CR2 register value */
;;;531      tmpcr2 =  TIMx->CR2;
00025e  8882              LDRH     r2,[r0,#4]
;;;532      
;;;533      /* Get the TIMx CCMR2 register value */
;;;534      tmpccmrx = TIMx->CCMR2;
000260  8b83              LDRH     r3,[r0,#0x1c]
;;;535        
;;;536      /* Reset the Output Compare Mode Bits */