📄 stm32f10x_tim.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 919] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\output\stm32f10x_tim.o --depend=.\output\stm32f10x_tim.d --device=DARMSTM --apcs=interwork -O1 -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -IC:\Keil\ARM\INC\ST\STM32F10x --omf_browse=.\output\stm32f10x_tim.crf ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_tim.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
TIM_DeInit PROC
;;;136 void TIM_DeInit(TIM_TypeDef* TIMx)
;;;137 {
000000 b510 PUSH {r4,lr}
;;;138 /* Check the parameters */
;;;139 assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;140
;;;141 switch (*(u32*)&TIMx)
000002 4afb LDR r2,|L1.1008|
000004 1a81 SUBS r1,r0,r2
000006 1513 ASRS r3,r2,#20
000008 14d4 ASRS r4,r2,#19
00000a 4290 CMP r0,r2
00000c d04f BEQ |L1.174|
00000e dc13 BGT |L1.56|
000010 f1b0f1b0 CMP r0,#0x40000000
000014 d02d BEQ |L1.114|
000016 49f7 LDR r1,|L1.1012|
000018 1840 ADDS r0,r0,r1
00001a d034 BEQ |L1.134|
00001c 4298 CMP r0,r3
00001e d03c BEQ |L1.154|
000020 42a0 CMP r0,r4
000022 d158 BNE |L1.214|
;;;142 {
;;;143 case TIM1_BASE:
;;;144 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
;;;145 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
;;;146 break;
;;;147
;;;148 case TIM2_BASE:
;;;149 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
;;;150 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
;;;151 break;
;;;152
;;;153 case TIM3_BASE:
;;;154 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
;;;155 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
;;;156 break;
;;;157
;;;158 case TIM4_BASE:
;;;159 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
;;;160 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
;;;161 break;
;;;162
;;;163 case TIM5_BASE:
;;;164 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
000024 2101 MOVS r1,#1
000026 2008 MOVS r0,#8
000028 f7fff7ff BL RCC_APB1PeriphResetCmd
;;;165 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
00002c 2100 MOVS r1,#0
00002e e8bde8bd POP {r4,lr}
000032 2008 MOVS r0,#8
000034 f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.56|
000038 4299 CMP r1,r3 ;141
00003a d042 BEQ |L1.194|
00003c f5b1f5b1 CMP r1,#0x11c00 ;141
000040 d00d BEQ |L1.94|
000042 f5b1f5b1 CMP r1,#0x12400 ;141
000046 d146 BNE |L1.214|
;;;166 break;
;;;167
;;;168 case TIM6_BASE:
;;;169 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
;;;170 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
;;;171 break;
;;;172
;;;173 case TIM7_BASE:
;;;174 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
;;;175 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
;;;176 break;
;;;177
;;;178 case TIM8_BASE:
;;;179 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
000048 2101 MOVS r1,#1
00004a 034c LSLS r4,r1,#13
00004c 4620 MOV r0,r4
00004e f7fff7ff BL RCC_APB2PeriphResetCmd
;;;180 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
000052 4620 MOV r0,r4
000054 e8bde8bd POP {r4,lr}
000058 2100 MOVS r1,#0
00005a f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.94|
00005e 2101 MOVS r1,#1 ;144
000060 4620 MOV r0,r4 ;144
000062 f7fff7ff BL RCC_APB2PeriphResetCmd
000066 4620 MOV r0,r4 ;145
000068 e8bde8bd POP {r4,lr} ;145
00006c 2100 MOVS r1,#0 ;145
00006e f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.114|
000072 2101 MOVS r1,#1 ;149
000074 4608 MOV r0,r1 ;149
000076 f7fff7ff BL RCC_APB1PeriphResetCmd
00007a 2100 MOVS r1,#0 ;150
00007c e8bde8bd POP {r4,lr} ;150
000080 2001 MOVS r0,#1 ;150
000082 f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.134|
000086 2101 MOVS r1,#1 ;154
000088 2002 MOVS r0,#2 ;154
00008a f7fff7ff BL RCC_APB1PeriphResetCmd
00008e 2100 MOVS r1,#0 ;155
000090 e8bde8bd POP {r4,lr} ;155
000094 2002 MOVS r0,#2 ;155
000096 f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.154|
00009a 2101 MOVS r1,#1 ;159
00009c 2004 MOVS r0,#4 ;159
00009e f7fff7ff BL RCC_APB1PeriphResetCmd
0000a2 2100 MOVS r1,#0 ;160
0000a4 e8bde8bd POP {r4,lr} ;160
0000a8 2004 MOVS r0,#4 ;160
0000aa f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.174|
0000ae 2101 MOVS r1,#1 ;169
0000b0 2010 MOVS r0,#0x10 ;169
0000b2 f7fff7ff BL RCC_APB1PeriphResetCmd
0000b6 2100 MOVS r1,#0 ;170
0000b8 e8bde8bd POP {r4,lr} ;170
0000bc 2010 MOVS r0,#0x10 ;170
0000be f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.194|
0000c2 2101 MOVS r1,#1 ;174
0000c4 2020 MOVS r0,#0x20 ;174
0000c6 f7fff7ff BL RCC_APB1PeriphResetCmd
0000ca 2100 MOVS r1,#0 ;175
0000cc e8bde8bd POP {r4,lr} ;175
0000d0 2020 MOVS r0,#0x20 ;175
0000d2 f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.214|
;;;181 break;
;;;182
;;;183 default:
;;;184 break;
;;;185 }
;;;186 }
0000d6 bd10 POP {r4,pc}
;;;187
ENDP
TIM_TimeBaseInit PROC
;;;207 /* Select the Counter Mode and set the clock division */
;;;208 TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
0000d8 8802 LDRH r2,[r0,#0]
0000da f002f002 AND r2,r2,#0x8f
0000de 8002 STRH r2,[r0,#0]
;;;209 TIMx->CR1 |= (u32)TIM_TimeBaseInitStruct->TIM_ClockDivision |
0000e0 88ca LDRH r2,[r1,#6]
0000e2 884b LDRH r3,[r1,#2]
0000e4 431a ORRS r2,r2,r3
0000e6 8803 LDRH r3,[r0,#0]
0000e8 431a ORRS r2,r2,r3
0000ea 8002 STRH r2,[r0,#0]
;;;210 TIM_TimeBaseInitStruct->TIM_CounterMode;
;;;211 /* Set the Autoreload value */
;;;212 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
0000ec 888a LDRH r2,[r1,#4]
0000ee 8582 STRH r2,[r0,#0x2c]
;;;213
;;;214 /* Set the Prescaler value */
;;;215 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
0000f0 880a LDRH r2,[r1,#0]
0000f2 8502 STRH r2,[r0,#0x28]
;;;216
;;;217 /* Generate an update event to reload the Prescaler value immediatly */
;;;218 TIMx->EGR = TIM_PSCReloadMode_Immediate;
0000f4 2201 MOVS r2,#1
0000f6 8282 STRH r2,[r0,#0x14]
;;;219
;;;220 if (((*(u32*)&TIMx) == TIM1_BASE) || ((*(u32*)&TIMx) == TIM8_BASE))
0000f8 4abf LDR r2,|L1.1016|
0000fa 4290 CMP r0,r2
0000fc d002 BEQ |L1.260|
0000fe 4abf LDR r2,|L1.1020|
000100 4290 CMP r0,r2
000102 d101 BNE |L1.264|
|L1.260|
;;;221 {
;;;222 /* Set the Repetition Counter value */
;;;223 TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
000104 7a09 LDRB r1,[r1,#8]
000106 8601 STRH r1,[r0,#0x30]
|L1.264|
;;;224 }
;;;225 }
000108 4770 BX lr
;;;226
ENDP
TIM_OC1Init PROC
;;;239 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
;;;240 {
00010a b530 PUSH {r4,r5,lr}
;;;241 u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
;;;242
;;;243 /* Check the parameters */
;;;244 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;245 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;246 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;247 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
;;;248
;;;249 /* Disable the Channel 1: Reset the CC1E Bit */
;;;250 TIMx->CCER &= CCER_CC1E_Reset;
00010c 8c02 LDRH r2,[r0,#0x20]
00010e f022f022 BIC r2,r2,#1
000112 8402 STRH r2,[r0,#0x20]
;;;251
;;;252 /* Get the TIMx CCER register value */
;;;253 tmpccer = TIMx->CCER;
000114 8c02 LDRH r2,[r0,#0x20]
;;;254
;;;255 /* Get the TIMx CR2 register value */
;;;256 tmpcr2 = TIMx->CR2;
000116 8883 LDRH r3,[r0,#4]
;;;257
;;;258 /* Get the TIMx CCMR1 register value */
;;;259 tmpccmrx = TIMx->CCMR1;
000118 8b04 LDRH r4,[r0,#0x18]
;;;260
;;;261 /* Reset the Output Compare Mode Bits */
;;;262 tmpccmrx &= CCMR_OC13M_Mask;
00011a f024f024 BIC r5,r4,#0x70
;;;263
;;;264 /* Select the Output Compare Mode */
;;;265 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
00011e 880c LDRH r4,[r1,#0]
000120 432c ORRS r4,r4,r5
;;;266
;;;267 /* Reset the Output Polarity level */
;;;268 tmpccer &= CCER_CC1P_Reset;
000122 f022f022 BIC r2,r2,#2
;;;269
;;;270 /* Set the Output Compare Polarity */
;;;271 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
000126 890d LDRH r5,[r1,#8]
000128 4315 ORRS r5,r5,r2
;;;272
;;;273 /* Set the Output State */
;;;274 tmpccer |= TIM_OCInitStruct->TIM_OutputState;
00012a 884a LDRH r2,[r1,#2]
00012c 432a ORRS r2,r2,r5
;;;275
;;;276 /* Set the Capture Compare Register value */
;;;277 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
00012e 88cd LDRH r5,[r1,#6]
000130 8685 STRH r5,[r0,#0x34]
;;;278
;;;279 if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
000132 4db1 LDR r5,|L1.1016|
000134 42a8 CMP r0,r5
000136 d002 BEQ |L1.318|
000138 4db0 LDR r5,|L1.1020|
00013a 42a8 CMP r0,r5
00013c d10f BNE |L1.350|
|L1.318|
;;;280 {
;;;281 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
;;;282 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
;;;283 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
;;;284 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;285
;;;286 /* Reset the Output N Polarity level */
;;;287 tmpccer &= CCER_CC1NP_Reset;
00013e f022f022 BIC r2,r2,#8
;;;288
;;;289 /* Set the Output N Polarity */
;;;290 tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
000142 894d LDRH r5,[r1,#0xa]
000144 4315 ORRS r5,r5,r2
;;;291
;;;292 /* Reset the Output N State */
;;;293 tmpccer &= CCER_CC1NE_Reset;
000146 f025f025 BIC r5,r5,#4
;;;294
;;;295 /* Set the Output N State */
;;;296 tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
00014a 888a LDRH r2,[r1,#4]
00014c 432a ORRS r2,r2,r5
;;;297
;;;298 /* Reset the Ouput Compare and Output Compare N IDLE State */
;;;299 tmpcr2 &= CR2_OIS1_Reset;
00014e f423f423 BIC r3,r3,#0x8100
;;;300 tmpcr2 &= CR2_OIS1N_Reset;
000152 f423f423 BIC r3,r3,#0x8200
;;;301
;;;302 /* Set the Output Idle state */
;;;303 tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
000156 898d LDRH r5,[r1,#0xc]
000158 431d ORRS r5,r5,r3
;;;304
;;;305 /* Set the Output N Idle state */
;;;306 tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
00015a 89cb LDRH r3,[r1,#0xe]
00015c 432b ORRS r3,r3,r5
|L1.350|
;;;307 }
;;;308 /* Write to TIMx CR2 */
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