📄 stm32f10x_usart.txt
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;;;275 /* Set CPOL bit according to USART_CPOL value */
;;;276 /* Set CPHA bit according to USART_CPHA value */
;;;277 /* Set LBCL bit according to USART_LastBit value */
;;;278 tmpreg |= (u32)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
000134 880b LDRH r3,[r1,#0]
000136 884c LDRH r4,[r1,#2]
000138 4323 ORRS r3,r3,r4
00013a 888c LDRH r4,[r1,#4]
00013c 88c9 LDRH r1,[r1,#6]
00013e 430c ORRS r4,r4,r1
000140 4323 ORRS r3,r3,r4
000142 4313 ORRS r3,r3,r2
;;;279 USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
;;;280
;;;281 /* Write to USART CR2 */
;;;282 USARTx->CR2 = (u16)tmpreg;
000144 8203 STRH r3,[r0,#0x10]
;;;283 }
000146 bd10 POP {r4,pc}
;;;284
ENDP
USART_ClockStructInit PROC
;;;295 /* USART_ClockInitStruct members default value */
;;;296 USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
000148 2100 MOVS r1,#0
00014a 8001 STRH r1,[r0,#0]
;;;297 USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
00014c 8041 STRH r1,[r0,#2]
;;;298 USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
00014e 8081 STRH r1,[r0,#4]
;;;299 USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
000150 80c1 STRH r1,[r0,#6]
;;;300 }
000152 4770 BX lr
;;;301
ENDP
USART_Cmd PROC
;;;318
;;;319 if (NewState != DISABLE)
000154 b121 CBZ r1,|L1.352|
;;;320 {
;;;321 /* Enable the selected USART by setting the UE bit in the CR1 register */
;;;322 USARTx->CR1 |= CR1_UE_Set;
000156 8981 LDRH r1,[r0,#0xc]
000158 f441f441 ORR r1,r1,#0x2000
00015c 8181 STRH r1,[r0,#0xc]
;;;323 }
;;;324 else
;;;325 {
;;;326 /* Disable the selected USART by clearing the UE bit in the CR1 register */
;;;327 USARTx->CR1 &= CR1_UE_Reset;
;;;328 }
;;;329 }
00015e 4770 BX lr
|L1.352|
000160 8981 LDRH r1,[r0,#0xc] ;327
000162 f421f421 BIC r1,r1,#0x2000 ;327
000166 8181 STRH r1,[r0,#0xc] ;327
000168 4770 BX lr
;;;330
ENDP
USART_ITConfig PROC
;;;356 void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState)
;;;357 {
00016a b510 PUSH {r4,lr}
;;;358 u32 usartreg = 0x00, itpos = 0x00, itmask = 0x00;
;;;359 u32 usartxbase = 0x00;
;;;360
;;;361 /* Check the parameters */
;;;362 assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;363 assert_param(IS_USART_CONFIG_IT(USART_IT));
;;;364 assert_param(IS_USART_PERIPH_IT(USARTx, USART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */
;;;365 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;366
;;;367 usartxbase = (*(u32*)&(USARTx));
;;;368
;;;369 /* Get the USART register index */
;;;370 usartreg = (((u8)USART_IT) >> 0x05);
00016c f3c1f3c1 UBFX r3,r1,#5,#3
;;;371
;;;372 /* Get the interrupt position */
;;;373 itpos = USART_IT & IT_Mask;
000170 f001f001 AND r4,r1,#0x1f
;;;374
;;;375 itmask = (((u32)0x01) << itpos);
000174 2101 MOVS r1,#1
000176 40a1 LSLS r1,r1,r4
;;;376
;;;377 if (usartreg == 0x01) /* The IT is in CR1 register */
000178 2b01 CMP r3,#1
00017a d101 BNE |L1.384|
;;;378 {
;;;379 usartxbase += 0x0C;
00017c 300c ADDS r0,r0,#0xc
00017e e004 B |L1.394|
|L1.384|
;;;380 }
;;;381 else if (usartreg == 0x02) /* The IT is in CR2 register */
000180 2b02 CMP r3,#2
000182 d101 BNE |L1.392|
;;;382 {
;;;383 usartxbase += 0x10;
000184 3010 ADDS r0,r0,#0x10
000186 e000 B |L1.394|
|L1.392|
;;;384 }
;;;385 else /* The IT is in CR3 register */
;;;386 {
;;;387 usartxbase += 0x14;
000188 3014 ADDS r0,r0,#0x14
|L1.394|
;;;388 }
;;;389 if (NewState != DISABLE)
00018a b11a CBZ r2,|L1.404|
;;;390 {
;;;391 *(vu32*)usartxbase |= itmask;
00018c 6802 LDR r2,[r0,#0]
00018e 430a ORRS r2,r2,r1
000190 6002 STR r2,[r0,#0]
;;;392 }
;;;393 else
;;;394 {
;;;395 *(vu32*)usartxbase &= ~itmask;
;;;396 }
;;;397 }
000192 bd10 POP {r4,pc}
|L1.404|
000194 6802 LDR r2,[r0,#0] ;395
000196 438a BICS r2,r2,r1 ;395
000198 6002 STR r2,[r0,#0] ;395
00019a bd10 POP {r4,pc}
;;;398
ENDP
USART_DMACmd PROC
;;;421
;;;422 if (NewState != DISABLE)
00019c b11a CBZ r2,|L1.422|
;;;423 {
;;;424 /* Enable the DMA transfer for selected requests by setting the DMAT and/or
;;;425 DMAR bits in the USART CR3 register */
;;;426 USARTx->CR3 |= USART_DMAReq;
00019e 8a82 LDRH r2,[r0,#0x14]
0001a0 430a ORRS r2,r2,r1
0001a2 8282 STRH r2,[r0,#0x14]
;;;427 }
;;;428 else
;;;429 {
;;;430 /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
;;;431 DMAR bits in the USART CR3 register */
;;;432 USARTx->CR3 &= (u16)~USART_DMAReq;
;;;433 }
;;;434 }
0001a4 4770 BX lr
|L1.422|
0001a6 8a82 LDRH r2,[r0,#0x14] ;432
0001a8 438a BICS r2,r2,r1 ;432
0001aa 8282 STRH r2,[r0,#0x14] ;432
0001ac 4770 BX lr
;;;435
ENDP
USART_SetAddress PROC
;;;452 /* Clear the USART address */
;;;453 USARTx->CR2 &= CR2_Address_Mask;
0001ae 8a02 LDRH r2,[r0,#0x10]
0001b0 f022f022 BIC r2,r2,#0xf
0001b4 8202 STRH r2,[r0,#0x10]
;;;454 /* Set the USART address node */
;;;455 USARTx->CR2 |= USART_Address;
0001b6 8a02 LDRH r2,[r0,#0x10]
0001b8 430a ORRS r2,r2,r1
0001ba 8202 STRH r2,[r0,#0x10]
;;;456 }
0001bc 4770 BX lr
;;;457
ENDP
USART_WakeUpConfig PROC
;;;476
;;;477 USARTx->CR1 &= CR1_WAKE_Mask;
0001be 8982 LDRH r2,[r0,#0xc]
0001c0 f422f422 BIC r2,r2,#0x800
0001c4 8182 STRH r2,[r0,#0xc]
;;;478 USARTx->CR1 |= USART_WakeUp;
0001c6 8982 LDRH r2,[r0,#0xc]
0001c8 430a ORRS r2,r2,r1
0001ca 8182 STRH r2,[r0,#0xc]
;;;479 }
0001cc 4770 BX lr
;;;480
ENDP
USART_ReceiverWakeUpCmd PROC
;;;497
;;;498 if (NewState != DISABLE)
0001ce b121 CBZ r1,|L1.474|
;;;499 {
;;;500 /* Enable the USART mute mode by setting the RWU bit in the CR1 register */
;;;501 USARTx->CR1 |= CR1_RWU_Set;
0001d0 8981 LDRH r1,[r0,#0xc]
0001d2 f041f041 ORR r1,r1,#2
0001d6 8181 STRH r1,[r0,#0xc]
;;;502 }
;;;503 else
;;;504 {
;;;505 /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
;;;506 USARTx->CR1 &= CR1_RWU_Reset;
;;;507 }
;;;508 }
0001d8 4770 BX lr
|L1.474|
0001da 8981 LDRH r1,[r0,#0xc] ;506
0001dc f021f021 BIC r1,r1,#2 ;506
0001e0 8181 STRH r1,[r0,#0xc] ;506
0001e2 4770 BX lr
;;;509
ENDP
USART_LINBreakDetectLengthConfig PROC
;;;529
;;;530 USARTx->CR2 &= CR2_LBDL_Mask;
0001e4 8a02 LDRH r2,[r0,#0x10]
0001e6 f022f022 BIC r2,r2,#0x20
0001ea 8202 STRH r2,[r0,#0x10]
;;;531 USARTx->CR2 |= USART_LINBreakDetectLength;
0001ec 8a02 LDRH r2,[r0,#0x10]
0001ee 430a ORRS r2,r2,r1
0001f0 8202 STRH r2,[r0,#0x10]
;;;532 }
0001f2 4770 BX lr
;;;533
ENDP
USART_LINCmd PROC
;;;550
;;;551 if (NewState != DISABLE)
0001f4 b121 CBZ r1,|L1.512|
;;;552 {
;;;553 /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
;;;554 USARTx->CR2 |= CR2_LINEN_Set;
0001f6 8a01 LDRH r1,[r0,#0x10]
0001f8 f441f441 ORR r1,r1,#0x4000
0001fc 8201 STRH r1,[r0,#0x10]
;;;555 }
;;;556 else
;;;557 {
;;;558 /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
;;;559 USARTx->CR2 &= CR2_LINEN_Reset;
;;;560 }
;;;561 }
0001fe 4770 BX lr
|L1.512|
000200 8a01 LDRH r1,[r0,#0x10] ;559
000202 f421f421 BIC r1,r1,#0x4000 ;559
000206 8201 STRH r1,[r0,#0x10] ;559
000208 4770 BX lr
;;;562
ENDP
USART_SendData PROC
;;;579 /* Transmit Data */
;;;580 USARTx->DR = (Data & (u16)0x01FF);
00020a f3c1f3c1 UBFX r1,r1,#0,#9
00020e 8081 STRH r1,[r0,#4]
;;;581 }
000210 4770 BX lr
;;;582
ENDP
USART_ReceiveData PROC
;;;597 /* Receive Data */
;;;598 return (u16)(USARTx->DR & (u16)0x01FF);
000212 8880 LDRH r0,[r0,#4]
000214 f3c0f3c0 UBFX r0,r0,#0,#9
;;;599 }
000218 4770 BX lr
;;;600
ENDP
USART_SendBreak PROC
;;;615 /* Send break characters */
;;;616 USARTx->CR1 |= CR1_SBK_Set;
00021a 8981 LDRH r1,[r0,#0xc]
00021c f041f041 ORR r1,r1,#1
000220 8181 STRH r1,[r0,#0xc]
;;;617 }
000222 4770 BX lr
;;;618
ENDP
USART_SetGuardTime PROC
;;;634 /* Clear the USART Guard time */
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