📄 stm32f10x_usart.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 919] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\output\stm32f10x_usart.o --depend=.\output\stm32f10x_usart.d --device=DARMSTM --apcs=interwork -O1 -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -IC:\Keil\ARM\INC\ST\STM32F10x --omf_browse=.\output\stm32f10x_usart.crf ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_usart.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
USART_DeInit PROC
;;;92 void USART_DeInit(USART_TypeDef* USARTx)
;;;93 {
000000 b510 PUSH {r4,lr}
;;;94 /* Check the parameters */
;;;95 assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;96
;;;97 switch (*(u32*)&USARTx)
000002 4ac1 LDR r2,|L1.776|
000004 1a81 SUBS r1,r0,r2
000006 1513 ASRS r3,r2,#20
000008 4290 CMP r0,r2
00000a d02b BEQ |L1.100|
00000c dc0f BGT |L1.46|
00000e 49bf LDR r1,|L1.780|
000010 1840 ADDS r0,r0,r1
000012 d01c BEQ |L1.78|
000014 4298 CMP r0,r3
000016 d13b BNE |L1.144|
;;;98 {
;;;99 case USART1_BASE:
;;;100 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
;;;101 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
;;;102 break;
;;;103
;;;104 case USART2_BASE:
;;;105 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
;;;106 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
;;;107 break;
;;;108
;;;109 case USART3_BASE:
;;;110 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
000018 2101 MOVS r1,#1
00001a 048c LSLS r4,r1,#18
00001c 4620 MOV r0,r4
00001e f7fff7ff BL RCC_APB1PeriphResetCmd
;;;111 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
000022 4620 MOV r0,r4
000024 e8bde8bd POP {r4,lr}
000028 2100 MOVS r1,#0
00002a f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.46|
00002e 4299 CMP r1,r3 ;97
000030 d023 BEQ |L1.122|
000032 f5b1f5b1 CMP r1,#0xec00 ;97
000036 d12b BNE |L1.144|
000038 2101 MOVS r1,#1 ;100
00003a 038c LSLS r4,r1,#14 ;100
00003c 4620 MOV r0,r4 ;100
00003e f7fff7ff BL RCC_APB2PeriphResetCmd
000042 4620 MOV r0,r4 ;101
000044 e8bde8bd POP {r4,lr} ;101
000048 2100 MOVS r1,#0 ;101
00004a f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.78|
00004e 2101 MOVS r1,#1 ;105
000050 044c LSLS r4,r1,#17 ;105
000052 4620 MOV r0,r4 ;105
000054 f7fff7ff BL RCC_APB1PeriphResetCmd
000058 4620 MOV r0,r4 ;106
00005a e8bde8bd POP {r4,lr} ;106
00005e 2100 MOVS r1,#0 ;106
000060 f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.100|
;;;112 break;
;;;113
;;;114 case UART4_BASE:
;;;115 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
000064 2101 MOVS r1,#1
000066 04cc LSLS r4,r1,#19
000068 4620 MOV r0,r4
00006a f7fff7ff BL RCC_APB1PeriphResetCmd
;;;116 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
00006e 4620 MOV r0,r4
000070 e8bde8bd POP {r4,lr}
000074 2100 MOVS r1,#0
000076 f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.122|
;;;117 break;
;;;118
;;;119 case UART5_BASE:
;;;120 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
00007a 2101 MOVS r1,#1
00007c 050c LSLS r4,r1,#20
00007e 4620 MOV r0,r4
000080 f7fff7ff BL RCC_APB1PeriphResetCmd
;;;121 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
000084 4620 MOV r0,r4
000086 e8bde8bd POP {r4,lr}
00008a 2100 MOVS r1,#0
00008c f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.144|
;;;122 break;
;;;123
;;;124 default:
;;;125 break;
;;;126 }
;;;127 }
000090 bd10 POP {r4,pc}
;;;128
ENDP
USART_Init PROC
;;;142 void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
;;;143 {
000092 b530 PUSH {r4,r5,lr}
000094 b085 SUB sp,sp,#0x14
000096 4604 MOV r4,r0
000098 460d MOV r5,r1
;;;144 u32 tmpreg = 0x00, apbclock = 0x00;
;;;145 u32 integerdivider = 0x00;
;;;146 u32 fractionaldivider = 0x00;
;;;147 u32 usartxbase = 0;
;;;148 RCC_ClocksTypeDef RCC_ClocksStatus;
;;;149
;;;150 /* Check the parameters */
;;;151 assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;152 assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
;;;153 assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
;;;154 assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
;;;155 assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
;;;156 assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
;;;157 assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
;;;158 /* The hardware flow control is available only for USART1, USART2 and USART3 */
;;;159 assert_param(IS_USART_PERIPH_HFC(USARTx, USART_InitStruct->USART_HardwareFlowControl));
;;;160
;;;161 usartxbase = (*(u32*)&USARTx);
;;;162
;;;163 /*---------------------------- USART CR2 Configuration -----------------------*/
;;;164 tmpreg = USARTx->CR2;
00009a 8a20 LDRH r0,[r4,#0x10]
;;;165 /* Clear STOP[13:12] bits */
;;;166 tmpreg &= CR2_STOP_CLEAR_Mask;
00009c f64cf64c MOV r1,#0xcfff
0000a0 4008 ANDS r0,r0,r1
;;;167
;;;168 /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
;;;169 /* Set STOP[13:12] bits according to USART_StopBits value */
;;;170 tmpreg |= (u32)USART_InitStruct->USART_StopBits;
0000a2 88e9 LDRH r1,[r5,#6]
0000a4 4301 ORRS r1,r1,r0
;;;171
;;;172 /* Write to USART CR2 */
;;;173 USARTx->CR2 = (u16)tmpreg;
0000a6 8221 STRH r1,[r4,#0x10]
;;;174
;;;175 /*---------------------------- USART CR1 Configuration -----------------------*/
;;;176 tmpreg = USARTx->CR1;
0000a8 89a0 LDRH r0,[r4,#0xc]
;;;177 /* Clear M, PCE, PS, TE and RE bits */
;;;178 tmpreg &= CR1_CLEAR_Mask;
0000aa f64ef64e MOV r1,#0xe9f3
0000ae 4008 ANDS r0,r0,r1
;;;179
;;;180 /* Configure the USART Word Length, Parity and mode ----------------------- */
;;;181 /* Set the M bits according to USART_WordLength value */
;;;182 /* Set PCE and PS bits according to USART_Parity value */
;;;183 /* Set TE and RE bits according to USART_Mode value */
;;;184 tmpreg |= (u32)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
0000b0 88a9 LDRH r1,[r5,#4]
0000b2 892a LDRH r2,[r5,#8]
0000b4 4311 ORRS r1,r1,r2
0000b6 896a LDRH r2,[r5,#0xa]
0000b8 4302 ORRS r2,r2,r0
0000ba 4311 ORRS r1,r1,r2
;;;185 USART_InitStruct->USART_Mode;
;;;186
;;;187 /* Write to USART CR1 */
;;;188 USARTx->CR1 = (u16)tmpreg;
0000bc 81a1 STRH r1,[r4,#0xc]
;;;189
;;;190 /*---------------------------- USART CR3 Configuration -----------------------*/
;;;191 tmpreg = USARTx->CR3;
0000be 8aa0 LDRH r0,[r4,#0x14]
;;;192 /* Clear CTSE and RTSE bits */
;;;193 tmpreg &= CR3_CLEAR_Mask;
0000c0 f64ff64f MOV r1,#0xfcff
0000c4 4008 ANDS r0,r0,r1
;;;194
;;;195 /* Configure the USART HFC -------------------------------------------------*/
;;;196 /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
;;;197 tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
0000c6 89a9 LDRH r1,[r5,#0xc]
0000c8 4301 ORRS r1,r1,r0
;;;198
;;;199 /* Write to USART CR3 */
;;;200 USARTx->CR3 = (u16)tmpreg;
0000ca 82a1 STRH r1,[r4,#0x14]
;;;201
;;;202 /*---------------------------- USART BRR Configuration -----------------------*/
;;;203 /* Configure the USART Baud Rate -------------------------------------------*/
;;;204 RCC_GetClocksFreq(&RCC_ClocksStatus);
0000cc 4668 MOV r0,sp
0000ce f7fff7ff BL RCC_GetClocksFreq
;;;205 if (usartxbase == USART1_BASE)
0000d2 488f LDR r0,|L1.784|
0000d4 4284 CMP r4,r0
0000d6 d101 BNE |L1.220|
;;;206 {
;;;207 apbclock = RCC_ClocksStatus.PCLK2_Frequency;
0000d8 9803 LDR r0,[sp,#0xc]
0000da e000 B |L1.222|
|L1.220|
;;;208 }
;;;209 else
;;;210 {
;;;211 apbclock = RCC_ClocksStatus.PCLK1_Frequency;
0000dc 9802 LDR r0,[sp,#8]
|L1.222|
;;;212 }
;;;213
;;;214 /* Determine the integer part */
;;;215 integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate)));
0000de 2119 MOVS r1,#0x19
0000e0 4348 MULS r0,r1,r0
0000e2 6829 LDR r1,[r5,#0]
0000e4 0089 LSLS r1,r1,#2
0000e6 fbb0fbb0 UDIV r0,r0,r1
;;;216 tmpreg = (integerdivider / 0x64) << 0x04;
0000ea 2364 MOVS r3,#0x64
0000ec fbb0fbb0 UDIV r1,r0,r3
0000f0 0109 LSLS r1,r1,#4
;;;217
;;;218 /* Determine the fractional part */
;;;219 fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04));
0000f2 090a LSRS r2,r1,#4
0000f4 f06ff06f MVN r5,#0x18
0000f8 436a MULS r2,r5,r2
0000fa eb00eb00 ADD r0,r0,r2,LSL #2
;;;220 tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((u8)0x0F);
0000fe 2232 MOVS r2,#0x32
000100 eb02eb02 ADD r0,r2,r0,LSL #4
000104 fbb0fbb0 UDIV r0,r0,r3
000108 f000f000 AND r0,r0,#0xf
00010c 4308 ORRS r0,r0,r1
;;;221
;;;222 /* Write to USART BRR */
;;;223 USARTx->BRR = (u16)tmpreg;
00010e 8120 STRH r0,[r4,#8]
;;;224 }
000110 b005 ADD sp,sp,#0x14
000112 bd30 POP {r4,r5,pc}
;;;225
ENDP
USART_StructInit PROC
;;;236 /* USART_InitStruct members default value */
;;;237 USART_InitStruct->USART_BaudRate = 9600;
000114 f44ff44f MOV r1,#0x2580
000118 6001 STR r1,[r0,#0]
;;;238 USART_InitStruct->USART_WordLength = USART_WordLength_8b;
00011a 2100 MOVS r1,#0
00011c 8081 STRH r1,[r0,#4]
;;;239 USART_InitStruct->USART_StopBits = USART_StopBits_1;
00011e 80c1 STRH r1,[r0,#6]
;;;240 USART_InitStruct->USART_Parity = USART_Parity_No ;
000120 8101 STRH r1,[r0,#8]
;;;241 USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
000122 220c MOVS r2,#0xc
000124 8142 STRH r2,[r0,#0xa]
;;;242 USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
000126 8181 STRH r1,[r0,#0xc]
;;;243 }
000128 4770 BX lr
;;;244
ENDP
USART_ClockInit PROC
;;;257 void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
;;;258 {
00012a b510 PUSH {r4,lr}
;;;259 u32 tmpreg = 0x00;
;;;260
;;;261 /* Check the parameters */
;;;262 assert_param(IS_USART_123_PERIPH(USARTx));
;;;263 assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
;;;264 assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
;;;265 assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
;;;266 assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
;;;267
;;;268 /*---------------------------- USART CR2 Configuration -----------------------*/
;;;269 tmpreg = USARTx->CR2;
00012c 8a02 LDRH r2,[r0,#0x10]
;;;270 /* Clear CLKEN, CPOL, CPHA and LBCL bits */
;;;271 tmpreg &= CR2_CLOCK_CLEAR_Mask;
00012e f24ff24f MOV r3,#0xf0ff
000132 401a ANDS r2,r2,r3
;;;272
;;;273 /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
;;;274 /* Set CLKEN bit according to USART_Clock value */
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