stm32f10x_i2c.txt
来自「stm32 ucos 精简移殖版本 不需作任何修改直接便可运行。包含串口 定时器」· 文本 代码 · 共 1,113 行 · 第 1/3 页
TXT
1,113 行
000154 4770 BX lr
|L1.342|
000156 8801 LDRH r1,[r0,#0] ;385
000158 f421f421 BIC r1,r1,#0x100 ;385
00015c 8001 STRH r1,[r0,#0] ;385
00015e 4770 BX lr
;;;388
ENDP
I2C_GenerateSTOP PROC
;;;403
;;;404 if (NewState != DISABLE)
000160 b121 CBZ r1,|L1.364|
;;;405 {
;;;406 /* Generate a STOP condition */
;;;407 I2Cx->CR1 |= CR1_STOP_Set;
000162 8801 LDRH r1,[r0,#0]
000164 f441f441 ORR r1,r1,#0x200
000168 8001 STRH r1,[r0,#0]
;;;408 }
;;;409 else
;;;410 {
;;;411 /* Disable the STOP condition generation */
;;;412 I2Cx->CR1 &= CR1_STOP_Reset;
;;;413 }
;;;414 }
00016a 4770 BX lr
|L1.364|
00016c 8801 LDRH r1,[r0,#0] ;412
00016e f421f421 BIC r1,r1,#0x200 ;412
000172 8001 STRH r1,[r0,#0] ;412
000174 4770 BX lr
;;;415
ENDP
I2C_AcknowledgeConfig PROC
;;;430
;;;431 if (NewState != DISABLE)
000176 b121 CBZ r1,|L1.386|
;;;432 {
;;;433 /* Enable the acknowledgement */
;;;434 I2Cx->CR1 |= CR1_ACK_Set;
000178 8801 LDRH r1,[r0,#0]
00017a f441f441 ORR r1,r1,#0x400
00017e 8001 STRH r1,[r0,#0]
;;;435 }
;;;436 else
;;;437 {
;;;438 /* Disable the acknowledgement */
;;;439 I2Cx->CR1 &= CR1_ACK_Reset;
;;;440 }
;;;441 }
000180 4770 BX lr
|L1.386|
000182 8801 LDRH r1,[r0,#0] ;439
000184 f421f421 BIC r1,r1,#0x400 ;439
000188 8001 STRH r1,[r0,#0] ;439
00018a 4770 BX lr
;;;442
ENDP
I2C_OwnAddress2Config PROC
;;;458 /* Get the old register value */
;;;459 tmpreg = I2Cx->OAR2;
00018c 8982 LDRH r2,[r0,#0xc]
;;;460 /* Reset I2Cx Own address2 bit [7:1] */
;;;461 tmpreg &= OAR2_ADD2_Reset;
00018e f022f022 BIC r2,r2,#0xfe
;;;462 /* Set I2Cx Own address2 */
;;;463 tmpreg |= (u16)(Address & (u16)0x00FE);
000192 f001f001 AND r1,r1,#0xfe
000196 4311 ORRS r1,r1,r2
;;;464 /* Store the new register value */
;;;465 I2Cx->OAR2 = tmpreg;
000198 8181 STRH r1,[r0,#0xc]
;;;466 }
00019a 4770 BX lr
;;;467
ENDP
I2C_DualAddressCmd PROC
;;;482
;;;483 if (NewState != DISABLE)
00019c b121 CBZ r1,|L1.424|
;;;484 {
;;;485 /* Enable dual addressing mode */
;;;486 I2Cx->OAR2 |= OAR2_ENDUAL_Set;
00019e 8981 LDRH r1,[r0,#0xc]
0001a0 f041f041 ORR r1,r1,#1
0001a4 8181 STRH r1,[r0,#0xc]
;;;487 }
;;;488 else
;;;489 {
;;;490 /* Disable dual addressing mode */
;;;491 I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
;;;492 }
;;;493 }
0001a6 4770 BX lr
|L1.424|
0001a8 8981 LDRH r1,[r0,#0xc] ;491
0001aa f021f021 BIC r1,r1,#1 ;491
0001ae 8181 STRH r1,[r0,#0xc] ;491
0001b0 4770 BX lr
;;;494
ENDP
I2C_GeneralCallCmd PROC
;;;509
;;;510 if (NewState != DISABLE)
0001b2 b121 CBZ r1,|L1.446|
;;;511 {
;;;512 /* Enable generall call */
;;;513 I2Cx->CR1 |= CR1_ENGC_Set;
0001b4 8801 LDRH r1,[r0,#0]
0001b6 f041f041 ORR r1,r1,#0x40
0001ba 8001 STRH r1,[r0,#0]
;;;514 }
;;;515 else
;;;516 {
;;;517 /* Disable generall call */
;;;518 I2Cx->CR1 &= CR1_ENGC_Reset;
;;;519 }
;;;520 }
0001bc 4770 BX lr
|L1.446|
0001be 8801 LDRH r1,[r0,#0] ;518
0001c0 f021f021 BIC r1,r1,#0x40 ;518
0001c4 8001 STRH r1,[r0,#0] ;518
0001c6 4770 BX lr
;;;521
ENDP
I2C_ITConfig PROC
;;;543
;;;544 if (NewState != DISABLE)
0001c8 b11a CBZ r2,|L1.466|
;;;545 {
;;;546 /* Enable the selected I2C interrupts */
;;;547 I2Cx->CR2 |= I2C_IT;
0001ca 8882 LDRH r2,[r0,#4]
0001cc 430a ORRS r2,r2,r1
0001ce 8082 STRH r2,[r0,#4]
;;;548 }
;;;549 else
;;;550 {
;;;551 /* Disable the selected I2C interrupts */
;;;552 I2Cx->CR2 &= (u16)~I2C_IT;
;;;553 }
;;;554 }
0001d0 4770 BX lr
|L1.466|
0001d2 8882 LDRH r2,[r0,#4] ;552
0001d4 438a BICS r2,r2,r1 ;552
0001d6 8082 STRH r2,[r0,#4] ;552
0001d8 4770 BX lr
;;;555
ENDP
I2C_SendData PROC
;;;569 /* Write in the DR register the data to be sent */
;;;570 I2Cx->DR = Data;
0001da 8201 STRH r1,[r0,#0x10]
;;;571 }
0001dc 4770 BX lr
;;;572
ENDP
I2C_ReceiveData PROC
;;;585 /* Return the data in the DR register */
;;;586 return (u8)I2Cx->DR;
0001de 8a00 LDRH r0,[r0,#0x10]
0001e0 b2c0 UXTB r0,r0
;;;587 }
0001e2 4770 BX lr
;;;588
ENDP
I2C_Send7bitAddress PROC
;;;608 /* Test on the direction to set/reset the read/write bit */
;;;609 if (I2C_Direction != I2C_Direction_Transmitter)
0001e4 b112 CBZ r2,|L1.492|
;;;610 {
;;;611 /* Set the address bit0 for read */
;;;612 Address |= OAR1_ADD0_Set;
0001e6 f041f041 ORR r1,r1,#1
0001ea e001 B |L1.496|
|L1.492|
;;;613 }
;;;614 else
;;;615 {
;;;616 /* Reset the address bit0 for write */
;;;617 Address &= OAR1_ADD0_Reset;
0001ec f001f001 AND r1,r1,#0xfe
|L1.496|
;;;618 }
;;;619 /* Send the address */
;;;620 I2Cx->DR = Address;
0001f0 8201 STRH r1,[r0,#0x10]
;;;621 }
0001f2 4770 BX lr
;;;622
ENDP
I2C_ReadRegister PROC
;;;646 /* Return the selected register value */
;;;647 return (*(vu16 *)(*((vu32 *)&I2Cx) + I2C_Register));
0001f4 5a40 LDRH r0,[r0,r1]
;;;648 }
0001f6 4770 BX lr
;;;649
ENDP
I2C_SoftwareResetCmd PROC
;;;664
;;;665 if (NewState != DISABLE)
0001f8 b121 CBZ r1,|L1.516|
;;;666 {
;;;667 /* Peripheral under reset */
;;;668 I2Cx->CR1 |= CR1_SWRST_Set;
0001fa 8801 LDRH r1,[r0,#0]
0001fc f441f441 ORR r1,r1,#0x8000
000200 8001 STRH r1,[r0,#0]
;;;669 }
;;;670 else
;;;671 {
;;;672 /* Peripheral not under reset */
;;;673 I2Cx->CR1 &= CR1_SWRST_Reset;
;;;674 }
;;;675 }
000202 4770 BX lr
|L1.516|
000204 8801 LDRH r1,[r0,#0] ;673
000206 f3c1f3c1 UBFX r1,r1,#0,#15 ;673
00020a 8001 STRH r1,[r0,#0] ;673
00020c 4770 BX lr
;;;676
ENDP
I2C_SMBusAlertConfig PROC
;;;693
;;;694 if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
00020e f5b1f5b1 CMP r1,#0x2000
000212 d104 BNE |L1.542|
;;;695 {
;;;696 /* Drive the SMBusAlert pin Low */
;;;697 I2Cx->CR1 |= I2C_SMBusAlert_Low;
000214 8801 LDRH r1,[r0,#0]
000216 f441f441 ORR r1,r1,#0x2000
00021a 8001 STRH r1,[r0,#0]
;;;698 }
;;;699 else
;;;700 {
;;;701 /* Drive the SMBusAlert pin High */
;;;702 I2Cx->CR1 &= I2C_SMBusAlert_High;
;;;703 }
;;;704 }
00021c 4770 BX lr
|L1.542|
00021e 8801 LDRH r1,[r0,#0] ;702
000220 f421f421 BIC r1,r1,#0x2000 ;702
000224 8001 STRH r1,[r0,#0] ;702
000226 4770 BX lr
;;;705
ENDP
I2C_TransmitPEC PROC
;;;720
;;;721 if (NewState != DISABLE)
000228 b121 CBZ r1,|L1.564|
;;;722 {
;;;723 /* Enable the selected I2C PEC transmission */
;;;724 I2Cx->CR1 |= CR1_PEC_Set;
00022a 8801 LDRH r1,[r0,#0]
00022c f441f441 ORR r1,r1,#0x1000
000230 8001 STRH r1,[r0,#0]
;;;725 }
;;;726 else
;;;727 {
;;;728 /* Disable the selected I2C PEC transmission */
;;;729 I2Cx->CR1 &= CR1_PEC_Reset;
;;;730 }
;;;731 }
000232 4770 BX lr
|L1.564|
000234 8801 LDRH r1,[r0,#0] ;729
000236 f421f421 BIC r1,r1,#0x1000 ;729
00023a 8001 STRH r1,[r0,#0] ;729
00023c 4770 BX lr
;;;732
ENDP
I2C_PECPositionConfig PROC
;;;751
;;;752 if (I2C_PECPosition == I2C_PECPosition_Next)
00023e f5b1f5b1 CMP r1,#0x800
000242 d104 BNE |L1.590|
;;;753 {
;;;754 /* Next byte in shift register is PEC */
;;;755 I2Cx->CR1 |= I2C_PECPosition_Next;
000244 8801 LDRH r1,[r0,#0]
000246 f441f441 ORR r1,r1,#0x800
00024a 8001 STRH r1,[r0,#0]
;;;756 }
;;;757 else
;;;758 {
;;;759 /* Current byte in shift register is PEC */
;;;760 I2Cx->CR1 &= I2C_PECPosition_Current;
;;;761 }
;;;762 }
00024c 4770 BX lr
|L1.590|
00024e 8801 LDRH r1,[r0,#0] ;760
000250 f421f421 BIC r1,r1,#0x800 ;760
000254 8001 STRH r1,[r0,#0] ;760
000256 4770 BX lr
;;;763
ENDP
I2C_CalculatePEC PROC
;;;779
;;;780 if (NewState != DISABLE)
000258 b121 CBZ r1,|L1.612|
;;;781 {
;;;782 /* Enable the selected I2C PEC calculation */
;;;783 I2Cx->CR1 |= CR1_ENPEC_Set;
00025a 8801 LDRH r1,[r0,#0]
00025c f041f041 ORR r1,r1,#0x20
000260 8001 STRH r1,[r0,#0]
;;;784 }
;;;785 else
;;;786 {
;;;787 /* Disable the selected I2C PEC calculation */
;;;788 I2Cx->CR1 &= CR1_ENPEC_Reset;
;;;789 }
;;;790 }
000262 4770 BX lr
|L1.612|
000264 8801 LDRH r1,[r0,#0] ;788
000266 f021f021 BIC r1,r1,#0x20 ;788
00026a 8001 STRH r1,[r0,#0] ;788
00026c 4770 BX lr
;;;791
ENDP
I2C_GetPEC PROC
;;;804 /* Return the selected I2C PEC value */
;;;805 return ((I2Cx->SR2) >> 8);
00026e 8b00 LDRH r0,[r0,#0x18]
000270 0a00 LSRS r0,r0,#8
;;;806 }
000272 4770 BX lr
;;;807
ENDP
I2C_ARPCmd PROC
;;;822
;;;823 if (NewState != DISABLE)
000274 b121 CBZ r1,|L1.640|
;;;824 {
;;;825 /* Enable the selected I2C ARP */
;;;826 I2Cx->CR1 |= CR1_ENARP_Set;
000276 8801 LDRH r1,[r0,#0]
000278 f041f041 ORR r1,r1,#0x10
00027c 8001 STRH r1,[r0,#0]
;;;827 }
;;;828 else
;;;829 {
;;;830 /* Disable the selected I2C ARP */
;;;831 I2Cx->CR1 &= CR1_ENARP_Reset;
;;;832 }
;;;833 }
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