📄 stm32f10x_i2c.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 919] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\output\stm32f10x_i2c.o --depend=.\output\stm32f10x_i2c.d --device=DARMSTM --apcs=interwork -O1 -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -IC:\Keil\ARM\INC\ST\STM32F10x --omf_browse=.\output\stm32f10x_i2c.crf ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_i2c.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
I2C_DeInit PROC
;;;111 void I2C_DeInit(I2C_TypeDef* I2Cx)
;;;112 {
000000 b510 PUSH {r4,lr}
;;;113 /* Check the parameters */
;;;114 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
;;;115
;;;116 switch (*(u32*)&I2Cx)
000002 49da LDR r1,|L1.876|
000004 1840 ADDS r0,r0,r1
000006 d00d BEQ |L1.36|
000008 f5b0f5b0 CMP r0,#0x400
00000c d115 BNE |L1.58|
;;;117 {
;;;118 case I2C1_BASE:
;;;119 /* Enable I2C1 reset state */
;;;120 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
;;;121 /* Release I2C1 from reset state */
;;;122 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
;;;123 break;
;;;124
;;;125 case I2C2_BASE:
;;;126 /* Enable I2C2 reset state */
;;;127 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
00000e 2101 MOVS r1,#1
000010 058c LSLS r4,r1,#22
000012 4620 MOV r0,r4
000014 f7fff7ff BL RCC_APB1PeriphResetCmd
;;;128 /* Release I2C2 from reset state */
;;;129 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
000018 4620 MOV r0,r4
00001a e8bde8bd POP {r4,lr}
00001e 2100 MOVS r1,#0
000020 f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.36|
000024 2101 MOVS r1,#1 ;120
000026 054c LSLS r4,r1,#21 ;120
000028 4620 MOV r0,r4 ;120
00002a f7fff7ff BL RCC_APB1PeriphResetCmd
00002e 4620 MOV r0,r4 ;122
000030 e8bde8bd POP {r4,lr} ;122
000034 2100 MOVS r1,#0 ;122
000036 f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.58|
;;;130 break;
;;;131
;;;132 default:
;;;133 break;
;;;134 }
;;;135 }
00003a bd10 POP {r4,pc}
;;;136
ENDP
I2C_Init PROC
;;;148 void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
;;;149 {
00003c b570 PUSH {r4-r6,lr}
00003e b086 SUB sp,sp,#0x18
000040 4604 MOV r4,r0
000042 460d MOV r5,r1
;;;150 u16 tmpreg = 0, freqrange = 0;
;;;151 u16 result = 0x04;
;;;152 u32 pclk1 = 8000000;
;;;153 RCC_ClocksTypeDef rcc_clocks;
;;;154
;;;155 /* Check the parameters */
;;;156 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
;;;157 assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
;;;158 assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
;;;159 assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
;;;160 assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
;;;161 assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
;;;162 assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
;;;163
;;;164 /*---------------------------- I2Cx CR2 Configuration ------------------------*/
;;;165 /* Get the I2Cx CR2 value */
;;;166 tmpreg = I2Cx->CR2;
000044 88a0 LDRH r0,[r4,#4]
;;;167 /* Clear frequency FREQ[5:0] bits */
;;;168 tmpreg &= CR2_FREQ_Reset;
000046 f020f020 BIC r6,r0,#0x3f
;;;169 /* Get pclk1 frequency value */
;;;170 RCC_GetClocksFreq(&rcc_clocks);
00004a a801 ADD r0,sp,#4
00004c f7fff7ff BL RCC_GetClocksFreq
;;;171 pclk1 = rcc_clocks.PCLK1_Frequency;
000050 9803 LDR r0,[sp,#0xc]
;;;172 /* Set frequency bits depending on pclk1 value */
;;;173 freqrange = (u16)(pclk1 / 1000000);
000052 49c7 LDR r1,|L1.880|
000054 fbb0fbb0 UDIV r1,r0,r1
000058 b289 UXTH r1,r1
;;;174 tmpreg |= freqrange;
00005a 430e ORRS r6,r6,r1
;;;175 /* Write to I2Cx CR2 */
;;;176 I2Cx->CR2 = tmpreg;
00005c 80a6 STRH r6,[r4,#4]
;;;177
;;;178 /*---------------------------- I2Cx CCR Configuration ------------------------*/
;;;179 /* Disable the selected I2C peripheral to configure TRISE */
;;;180 I2Cx->CR1 &= CR1_PE_Reset;
00005e 8822 LDRH r2,[r4,#0]
000060 f022f022 BIC r2,r2,#1
000064 8022 STRH r2,[r4,#0]
;;;181
;;;182 /* Reset tmpreg value */
;;;183 /* Clear F/S, DUTY and CCR[11:0] bits */
;;;184 tmpreg = 0;
;;;185
;;;186 /* Configure speed in standard mode */
;;;187 if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
000066 4bc3 LDR r3,|L1.884|
000068 68ea LDR r2,[r5,#0xc]
00006a 429a CMP r2,r3
00006c d809 BHI |L1.130|
;;;188 {
;;;189 /* Standard mode speed calculate */
;;;190 result = (u16)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
00006e 0052 LSLS r2,r2,#1
000070 fbb0fbb0 UDIV r0,r0,r2
000074 b280 UXTH r0,r0
;;;191 /* Test if CCR value is under 0x4*/
;;;192 if (result < 0x04)
000076 2804 CMP r0,#4
000078 d200 BCS |L1.124|
;;;193 {
;;;194 /* Set minimum allowed value */
;;;195 result = 0x04;
00007a 2004 MOVS r0,#4
|L1.124|
;;;196 }
;;;197 /* Set speed value for standard mode */
;;;198 tmpreg |= result;
;;;199 /* Set Maximum Rise Time for standard mode */
;;;200 I2Cx->TRISE = freqrange + 1;
00007c 1c49 ADDS r1,r1,#1
00007e 8421 STRH r1,[r4,#0x20]
000080 e020 B |L1.196|
|L1.130|
;;;201 }
;;;202 /* Configure speed in fast mode */
;;;203 else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
;;;204 {
;;;205 if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
000082 886b LDRH r3,[r5,#2]
000084 f5a3f5a3 SUB r6,r3,#0xbf00
000088 3eff SUBS r6,r6,#0xff
00008a d105 BNE |L1.152|
;;;206 {
;;;207 /* Fast mode speed calculate: Tlow/Thigh = 2 */
;;;208 result = (u16)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
00008c eb02eb02 ADD r2,r2,r2,LSL #1
000090 fbb0fbb0 UDIV r0,r0,r2
000094 b280 UXTH r0,r0
000096 e006 B |L1.166|
|L1.152|
;;;209 }
;;;210 else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
;;;211 {
;;;212 /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
;;;213 result = (u16)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
000098 2319 MOVS r3,#0x19
00009a 435a MULS r2,r3,r2
00009c fbb0fbb0 UDIV r0,r0,r2
0000a0 b280 UXTH r0,r0
;;;214 /* Set DUTY bit */
;;;215 result |= I2C_DutyCycle_16_9;
0000a2 f440f440 ORR r0,r0,#0x4000
|L1.166|
;;;216 }
;;;217 /* Test if CCR value is under 0x1*/
;;;218 if ((result & CCR_CCR_Set) == 0)
0000a6 0502 LSLS r2,r0,#20
0000a8 d101 BNE |L1.174|
;;;219 {
;;;220 /* Set minimum allowed value */
;;;221 result |= (u16)0x0001;
0000aa f040f040 ORR r0,r0,#1
|L1.174|
;;;222 }
;;;223 /* Set speed value and set F/S bit for fast mode */
;;;224 tmpreg |= result | CCR_FS_Set;
0000ae f440f440 ORR r0,r0,#0x8000
;;;225 /* Set Maximum Rise Time for fast mode */
;;;226 I2Cx->TRISE = (u16)(((freqrange * 300) / 1000) + 1);
0000b2 f44ff44f MOV r2,#0x12c
0000b6 4351 MULS r1,r2,r1
0000b8 f44ff44f MOV r2,#0x3e8
0000bc fbb1fbb1 UDIV r1,r1,r2
0000c0 1c49 ADDS r1,r1,#1
0000c2 8421 STRH r1,[r4,#0x20]
|L1.196|
;;;227 }
;;;228 /* Write to I2Cx CCR */
;;;229 I2Cx->CCR = tmpreg;
0000c4 83a0 STRH r0,[r4,#0x1c]
;;;230
;;;231 /* Enable the selected I2C peripheral */
;;;232 I2Cx->CR1 |= CR1_PE_Set;
0000c6 8820 LDRH r0,[r4,#0]
0000c8 f040f040 ORR r0,r0,#1
0000cc 8020 STRH r0,[r4,#0]
;;;233
;;;234 /*---------------------------- I2Cx CR1 Configuration ------------------------*/
;;;235 /* Get the I2Cx CR1 value */
;;;236 tmpreg = I2Cx->CR1;
0000ce 8820 LDRH r0,[r4,#0]
;;;237 /* Clear ACK, SMBTYPE and SMBUS bits */
;;;238 tmpreg &= CR1_CLEAR_Mask;
0000d0 f64ff64f MOV r1,#0xfbf5
0000d4 4008 ANDS r0,r0,r1
;;;239 /* Configure I2Cx: mode and acknowledgement */
;;;240 /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
;;;241 /* Set ACK bit according to I2C_Ack value */
;;;242 tmpreg |= (u16)((u32)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
0000d6 8829 LDRH r1,[r5,#0]
0000d8 88ea LDRH r2,[r5,#6]
0000da 4311 ORRS r1,r1,r2
0000dc 4301 ORRS r1,r1,r0
;;;243 /* Write to I2Cx CR1 */
;;;244 I2Cx->CR1 = tmpreg;
0000de 8021 STRH r1,[r4,#0]
;;;245
;;;246 /*---------------------------- I2Cx OAR1 Configuration -----------------------*/
;;;247 /* Set I2Cx Own Address1 and acknowledged address */
;;;248 I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
0000e0 8928 LDRH r0,[r5,#8]
0000e2 88a9 LDRH r1,[r5,#4]
0000e4 4308 ORRS r0,r0,r1
0000e6 8120 STRH r0,[r4,#8]
;;;249 }
0000e8 b006 ADD sp,sp,#0x18
0000ea bd70 POP {r4-r6,pc}
;;;250
ENDP
I2C_StructInit PROC
;;;262 /* Initialize the I2C_Mode member */
;;;263 I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
0000ec 2100 MOVS r1,#0
0000ee 8001 STRH r1,[r0,#0]
;;;264
;;;265 /* Initialize the I2C_DutyCycle member */
;;;266 I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
0000f0 f64bf64b MOV r2,#0xbfff
0000f4 8042 STRH r2,[r0,#2]
;;;267
;;;268 /* Initialize the I2C_OwnAddress1 member */
;;;269 I2C_InitStruct->I2C_OwnAddress1 = 0;
0000f6 8081 STRH r1,[r0,#4]
;;;270
;;;271 /* Initialize the I2C_Ack member */
;;;272 I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
0000f8 80c1 STRH r1,[r0,#6]
;;;273
;;;274 /* Initialize the I2C_AcknowledgedAddress member */
;;;275 I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
0000fa f44ff44f MOV r1,#0x4000
0000fe 8101 STRH r1,[r0,#8]
;;;276
;;;277 /* initialize the I2C_ClockSpeed member */
;;;278 I2C_InitStruct->I2C_ClockSpeed = 5000;
000100 f241f241 MOV r1,#0x1388
000104 60c1 STR r1,[r0,#0xc]
;;;279 }
000106 4770 BX lr
;;;280
ENDP
I2C_Cmd PROC
;;;295
;;;296 if (NewState != DISABLE)
000108 b121 CBZ r1,|L1.276|
;;;297 {
;;;298 /* Enable the selected I2C peripheral */
;;;299 I2Cx->CR1 |= CR1_PE_Set;
00010a 8801 LDRH r1,[r0,#0]
00010c f041f041 ORR r1,r1,#1
000110 8001 STRH r1,[r0,#0]
;;;300 }
;;;301 else
;;;302 {
;;;303 /* Disable the selected I2C peripheral */
;;;304 I2Cx->CR1 &= CR1_PE_Reset;
;;;305 }
;;;306 }
000112 4770 BX lr
|L1.276|
000114 8801 LDRH r1,[r0,#0] ;304
000116 f021f021 BIC r1,r1,#1 ;304
00011a 8001 STRH r1,[r0,#0] ;304
00011c 4770 BX lr
;;;307
ENDP
I2C_DMACmd PROC
;;;322
;;;323 if (NewState != DISABLE)
00011e b121 CBZ r1,|L1.298|
;;;324 {
;;;325 /* Enable the selected I2C DMA requests */
;;;326 I2Cx->CR2 |= CR2_DMAEN_Set;
000120 8881 LDRH r1,[r0,#4]
000122 f441f441 ORR r1,r1,#0x800
000126 8081 STRH r1,[r0,#4]
;;;327 }
;;;328 else
;;;329 {
;;;330 /* Disable the selected I2C DMA requests */
;;;331 I2Cx->CR2 &= CR2_DMAEN_Reset;
;;;332 }
;;;333 }
000128 4770 BX lr
|L1.298|
00012a 8881 LDRH r1,[r0,#4] ;331
00012c f421f421 BIC r1,r1,#0x800 ;331
000130 8081 STRH r1,[r0,#4] ;331
000132 4770 BX lr
;;;334
ENDP
I2C_DMALastTransferCmd PROC
;;;349
;;;350 if (NewState != DISABLE)
000134 b121 CBZ r1,|L1.320|
;;;351 {
;;;352 /* Next DMA transfer is the last transfer */
;;;353 I2Cx->CR2 |= CR2_LAST_Set;
000136 8881 LDRH r1,[r0,#4]
000138 f441f441 ORR r1,r1,#0x1000
00013c 8081 STRH r1,[r0,#4]
;;;354 }
;;;355 else
;;;356 {
;;;357 /* Next DMA transfer is not the last transfer */
;;;358 I2Cx->CR2 &= CR2_LAST_Reset;
;;;359 }
;;;360 }
00013e 4770 BX lr
|L1.320|
000140 8881 LDRH r1,[r0,#4] ;358
000142 f421f421 BIC r1,r1,#0x1000 ;358
000146 8081 STRH r1,[r0,#4] ;358
000148 4770 BX lr
;;;361
ENDP
I2C_GenerateSTART PROC
;;;376
;;;377 if (NewState != DISABLE)
00014a b121 CBZ r1,|L1.342|
;;;378 {
;;;379 /* Generate a START condition */
;;;380 I2Cx->CR1 |= CR1_START_Set;
00014c 8801 LDRH r1,[r0,#0]
00014e f441f441 ORR r1,r1,#0x100
000152 8001 STRH r1,[r0,#0]
;;;381 }
;;;382 else
;;;383 {
;;;384 /* Disable the START condition generation */
;;;385 I2Cx->CR1 &= CR1_START_Reset;
;;;386 }
;;;387 }
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