📄 stm32f10x_rcc.txt
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;;;721 presc = APBAHBPrescTable[tmp];
0001e8 4b3d LDR r3,|L1.736|
0001ea 5c5c LDRB r4,[r3,r1]
;;;722
;;;723 /* HCLK clock frequency */
;;;724 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
0001ec 6801 LDR r1,[r0,#0]
0001ee 40e1 LSRS r1,r1,r4
0001f0 6041 STR r1,[r0,#4]
;;;725
;;;726 /* Get PCLK1 prescaler */
;;;727 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
0001f2 6854 LDR r4,[r2,#4]
0001f4 f404f404 AND r4,r4,#0x700
;;;728 tmp = tmp >> 8;
0001f8 0a24 LSRS r4,r4,#8
;;;729 presc = APBAHBPrescTable[tmp];
0001fa 5d1c LDRB r4,[r3,r4]
;;;730
;;;731 /* PCLK1 clock frequency */
;;;732 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
0001fc fa21fa21 LSR r4,r1,r4
000200 6084 STR r4,[r0,#8]
;;;733
;;;734 /* Get PCLK2 prescaler */
;;;735 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
000202 6854 LDR r4,[r2,#4]
000204 f404f404 AND r4,r4,#0x3800
;;;736 tmp = tmp >> 11;
000208 0ae4 LSRS r4,r4,#11
;;;737 presc = APBAHBPrescTable[tmp];
00020a 5d1b LDRB r3,[r3,r4]
;;;738
;;;739 /* PCLK2 clock frequency */
;;;740 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
00020c 40d9 LSRS r1,r1,r3
00020e 60c1 STR r1,[r0,#0xc]
;;;741
;;;742 /* Get ADCCLK prescaler */
;;;743 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
000210 6852 LDR r2,[r2,#4]
000212 f402f402 AND r2,r2,#0xc000
;;;744 tmp = tmp >> 14;
000216 0b92 LSRS r2,r2,#14
;;;745 presc = ADCPrescTable[tmp];
000218 4b31 LDR r3,|L1.736|
00021a 1f1b SUBS r3,r3,#4
00021c 5c9a LDRB r2,[r3,r2]
;;;746
;;;747 /* ADCCLK clock frequency */
;;;748 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
00021e fbb1fbb1 UDIV r1,r1,r2
000222 6101 STR r1,[r0,#0x10]
;;;749 }
000224 bd30 POP {r4,r5,pc}
;;;750
ENDP
RCC_AHBPeriphClockCmd PROC
;;;774
;;;775 if (NewState != DISABLE)
000226 4a26 LDR r2,|L1.704|
000228 b119 CBZ r1,|L1.562|
;;;776 {
;;;777 RCC->AHBENR |= RCC_AHBPeriph;
00022a 6951 LDR r1,[r2,#0x14]
00022c 4301 ORRS r1,r1,r0
00022e 6151 STR r1,[r2,#0x14]
;;;778 }
;;;779 else
;;;780 {
;;;781 RCC->AHBENR &= ~RCC_AHBPeriph;
;;;782 }
;;;783 }
000230 4770 BX lr
|L1.562|
000232 6951 LDR r1,[r2,#0x14] ;781
000234 4381 BICS r1,r1,r0 ;781
000236 6151 STR r1,[r2,#0x14] ;781
000238 4770 BX lr
;;;784
ENDP
RCC_APB2PeriphClockCmd PROC
;;;807
;;;808 if (NewState != DISABLE)
00023a 4a21 LDR r2,|L1.704|
00023c b119 CBZ r1,|L1.582|
;;;809 {
;;;810 RCC->APB2ENR |= RCC_APB2Periph;
00023e 6991 LDR r1,[r2,#0x18]
000240 4301 ORRS r1,r1,r0
000242 6191 STR r1,[r2,#0x18]
;;;811 }
;;;812 else
;;;813 {
;;;814 RCC->APB2ENR &= ~RCC_APB2Periph;
;;;815 }
;;;816 }
000244 4770 BX lr
|L1.582|
000246 6991 LDR r1,[r2,#0x18] ;814
000248 4381 BICS r1,r1,r0 ;814
00024a 6191 STR r1,[r2,#0x18] ;814
00024c 4770 BX lr
;;;817
ENDP
RCC_APB1PeriphClockCmd PROC
;;;841
;;;842 if (NewState != DISABLE)
00024e 4a1c LDR r2,|L1.704|
000250 b119 CBZ r1,|L1.602|
;;;843 {
;;;844 RCC->APB1ENR |= RCC_APB1Periph;
000252 69d1 LDR r1,[r2,#0x1c]
000254 4301 ORRS r1,r1,r0
000256 61d1 STR r1,[r2,#0x1c]
;;;845 }
;;;846 else
;;;847 {
;;;848 RCC->APB1ENR &= ~RCC_APB1Periph;
;;;849 }
;;;850 }
000258 4770 BX lr
|L1.602|
00025a 69d1 LDR r1,[r2,#0x1c] ;848
00025c 4381 BICS r1,r1,r0 ;848
00025e 61d1 STR r1,[r2,#0x1c] ;848
000260 4770 BX lr
;;;851
ENDP
RCC_APB2PeriphResetCmd PROC
;;;873
;;;874 if (NewState != DISABLE)
000262 4a17 LDR r2,|L1.704|
000264 b119 CBZ r1,|L1.622|
;;;875 {
;;;876 RCC->APB2RSTR |= RCC_APB2Periph;
000266 68d1 LDR r1,[r2,#0xc]
000268 4301 ORRS r1,r1,r0
00026a 60d1 STR r1,[r2,#0xc]
;;;877 }
;;;878 else
;;;879 {
;;;880 RCC->APB2RSTR &= ~RCC_APB2Periph;
;;;881 }
;;;882 }
00026c 4770 BX lr
|L1.622|
00026e 68d1 LDR r1,[r2,#0xc] ;880
000270 4381 BICS r1,r1,r0 ;880
000272 60d1 STR r1,[r2,#0xc] ;880
000274 4770 BX lr
;;;883
ENDP
RCC_APB1PeriphResetCmd PROC
;;;906
;;;907 if (NewState != DISABLE)
000276 4a12 LDR r2,|L1.704|
000278 b119 CBZ r1,|L1.642|
;;;908 {
;;;909 RCC->APB1RSTR |= RCC_APB1Periph;
00027a 6911 LDR r1,[r2,#0x10]
00027c 4301 ORRS r1,r1,r0
00027e 6111 STR r1,[r2,#0x10]
;;;910 }
;;;911 else
;;;912 {
;;;913 RCC->APB1RSTR &= ~RCC_APB1Periph;
;;;914 }
;;;915 }
000280 4770 BX lr
|L1.642|
000282 6911 LDR r1,[r2,#0x10] ;913
000284 4381 BICS r1,r1,r0 ;913
000286 6111 STR r1,[r2,#0x10] ;913
000288 4770 BX lr
;;;916
ENDP
RCC_BackupResetCmd PROC
;;;929
;;;930 *(vu32 *) BDCR_BDRST_BB = (u32)NewState;
00028a 4912 LDR r1,|L1.724|
00028c 3940 SUBS r1,r1,#0x40
00028e 6008 STR r0,[r1,#0]
;;;931 }
000290 4770 BX lr
;;;932
ENDP
RCC_ClockSecuritySystemCmd PROC
;;;945
;;;946 *(vu32 *) CR_CSSON_BB = (u32)NewState;
000292 490f LDR r1,|L1.720|
000294 64c8 STR r0,[r1,#0x4c]
;;;947 }
000296 4770 BX lr
;;;948
ENDP
RCC_MCOConfig PROC
;;;967 /* Perform Byte access to MCO[2:0] bits to select the MCO source */
;;;968 *(vu8 *) CFGR_BYTE4_ADDRESS = RCC_MCO;
000298 4909 LDR r1,|L1.704|
00029a 71c8 STRB r0,[r1,#7]
;;;969 }
00029c 4770 BX lr
;;;970
ENDP
RCC_ClearFlag PROC
;;;1043 /* Set RMVF bit to clear the reset flags */
;;;1044 RCC->CSR |= CSR_RMVF_Set;
00029e 4808 LDR r0,|L1.704|
0002a0 6a41 LDR r1,[r0,#0x24]
0002a2 f041f041 ORR r1,r1,#0x1000000
0002a6 6241 STR r1,[r0,#0x24]
;;;1045 }
0002a8 4770 BX lr
;;;1046
ENDP
RCC_GetITStatus PROC
;;;1061 ITStatus RCC_GetITStatus(u8 RCC_IT)
;;;1062 {
0002aa 4602 MOV r2,r0
;;;1063 ITStatus bitstatus = RESET;
0002ac 2000 MOVS r0,#0
;;;1064
;;;1065 /* Check the parameters */
;;;1066 assert_param(IS_RCC_GET_IT(RCC_IT));
;;;1067
;;;1068 /* Check the status of the specified RCC interrupt */
;;;1069 if ((RCC->CIR & RCC_IT) != (u32)RESET)
0002ae 4904 LDR r1,|L1.704|
0002b0 6889 LDR r1,[r1,#8]
0002b2 4211 TST r1,r2
0002b4 d000 BEQ |L1.696|
;;;1070 {
;;;1071 bitstatus = SET;
0002b6 2001 MOVS r0,#1
|L1.696|
;;;1072 }
;;;1073 else
;;;1074 {
;;;1075 bitstatus = RESET;
;;;1076 }
;;;1077
;;;1078 /* Return the RCC_IT status */
;;;1079 return bitstatus;
;;;1080 }
0002b8 4770 BX lr
;;;1081
ENDP
RCC_ClearITPendingBit PROC
;;;1102 pending bits */
;;;1103 *(vu8 *) CIR_BYTE3_ADDRESS = RCC_IT;
0002ba 4901 LDR r1,|L1.704|
0002bc 7288 STRB r0,[r1,#0xa]
;;;1104 }
0002be 4770 BX lr
;;;1105
ENDP
|L1.704|
0002c0 40021000 DCD 0x40021000
|L1.708|
0002c4 f8ff0000 DCD 0xf8ff0000
|L1.712|
0002c8 fef6ffff DCD 0xfef6ffff
|L1.716|
0002cc 00000000 DCD ||.data||
|L1.720|
0002d0 42420000 DCD 0x42420000
|L1.724|
0002d4 42420480 DCD 0x42420480
|L1.728|
0002d8 007a1200 DCD 0x007a1200
|L1.732|
0002dc 003d0900 DCD 0x003d0900
|L1.736|
0002e0 00000004 DCD ||.constdata||+0x4
AREA ||.data||, DATA, ALIGN=2
HSEStatus
000000 00000000 DCB 0x00,0x00,0x00,0x00
StartUpCounter
000004 00000000 DCD 0x00000000
AREA ||.constdata||, DATA, READONLY, ALIGN=0
ADCPrescTable
000000 02040608 DCB 0x02,0x04,0x06,0x08
APBAHBPrescTable
000004 00000000 DCB 0x00,0x00,0x00,0x00
000008 01020304 DCB 0x01,0x02,0x03,0x04
00000c 01020304 DCB 0x01,0x02,0x03,0x04
000010 06070809 DCB 0x06,0x07,0x08,0x09
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