📄 stm32f10x_rcc.txt
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0000f8 6840 LDR r0,[r0,#4]
0000fa f000f000 AND r0,r0,#0xc
;;;369 }
0000fe 4770 BX lr
;;;370
ENDP
RCC_HCLKConfig PROC
;;;395
;;;396 tmpreg = RCC->CFGR;
000100 4a6f LDR r2,|L1.704|
000102 6851 LDR r1,[r2,#4]
;;;397
;;;398 /* Clear HPRE[3:0] bits */
;;;399 tmpreg &= CFGR_HPRE_Reset_Mask;
000104 f021f021 BIC r1,r1,#0xf0
;;;400
;;;401 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
;;;402 tmpreg |= RCC_SYSCLK;
000108 4301 ORRS r1,r1,r0
;;;403
;;;404 /* Store the new value */
;;;405 RCC->CFGR = tmpreg;
00010a 6051 STR r1,[r2,#4]
;;;406 }
00010c 4770 BX lr
;;;407
ENDP
RCC_PCLK1Config PROC
;;;428
;;;429 tmpreg = RCC->CFGR;
00010e 4a6c LDR r2,|L1.704|
000110 6851 LDR r1,[r2,#4]
;;;430
;;;431 /* Clear PPRE1[2:0] bits */
;;;432 tmpreg &= CFGR_PPRE1_Reset_Mask;
000112 f421f421 BIC r1,r1,#0x700
;;;433
;;;434 /* Set PPRE1[2:0] bits according to RCC_HCLK value */
;;;435 tmpreg |= RCC_HCLK;
000116 4301 ORRS r1,r1,r0
;;;436
;;;437 /* Store the new value */
;;;438 RCC->CFGR = tmpreg;
000118 6051 STR r1,[r2,#4]
;;;439 }
00011a 4770 BX lr
;;;440
ENDP
RCC_PCLK2Config PROC
;;;461
;;;462 tmpreg = RCC->CFGR;
00011c 4a68 LDR r2,|L1.704|
00011e 6851 LDR r1,[r2,#4]
;;;463
;;;464 /* Clear PPRE2[2:0] bits */
;;;465 tmpreg &= CFGR_PPRE2_Reset_Mask;
000120 f421f421 BIC r1,r1,#0x3800
;;;466
;;;467 /* Set PPRE2[2:0] bits according to RCC_HCLK value */
;;;468 tmpreg |= RCC_HCLK << 3;
000124 ea41ea41 ORR r0,r1,r0,LSL #3
;;;469
;;;470 /* Store the new value */
;;;471 RCC->CFGR = tmpreg;
000128 6050 STR r0,[r2,#4]
;;;472 }
00012a 4770 BX lr
;;;473
ENDP
RCC_ITConfig PROC
;;;495
;;;496 if (NewState != DISABLE)
00012c 4a64 LDR r2,|L1.704|
00012e b119 CBZ r1,|L1.312|
;;;497 {
;;;498 /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
;;;499 *(vu8 *) CIR_BYTE2_ADDRESS |= RCC_IT;
000130 7a51 LDRB r1,[r2,#9]
000132 4301 ORRS r1,r1,r0
000134 7251 STRB r1,[r2,#9]
;;;500 }
;;;501 else
;;;502 {
;;;503 /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
;;;504 *(vu8 *) CIR_BYTE2_ADDRESS &= (u8)~RCC_IT;
;;;505 }
;;;506 }
000136 4770 BX lr
|L1.312|
000138 7a51 LDRB r1,[r2,#9] ;504
00013a 4381 BICS r1,r1,r0 ;504
00013c 7251 STRB r1,[r2,#9] ;504
00013e 4770 BX lr
;;;507
ENDP
RCC_USBCLKConfig PROC
;;;525
;;;526 *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;
000140 4963 LDR r1,|L1.720|
000142 31d8 ADDS r1,r1,#0xd8
000144 6008 STR r0,[r1,#0]
;;;527 }
000146 4770 BX lr
;;;528
ENDP
RCC_ADCCLKConfig PROC
;;;548
;;;549 tmpreg = RCC->CFGR;
000148 4a5d LDR r2,|L1.704|
00014a 6851 LDR r1,[r2,#4]
;;;550
;;;551 /* Clear ADCPRE[1:0] bits */
;;;552 tmpreg &= CFGR_ADCPRE_Reset_Mask;
00014c f421f421 BIC r1,r1,#0xc000
;;;553
;;;554 /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
;;;555 tmpreg |= RCC_PCLK2;
000150 4301 ORRS r1,r1,r0
;;;556
;;;557 /* Store the new value */
;;;558 RCC->CFGR = tmpreg;
000152 6051 STR r1,[r2,#4]
;;;559 }
000154 4770 BX lr
;;;560
ENDP
RCC_LSEConfig PROC
;;;579 /* Reset LSEON bit */
;;;580 *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF;
000156 495a LDR r1,|L1.704|
000158 2200 MOVS r2,#0
00015a 3120 ADDS r1,r1,#0x20
00015c 700a STRB r2,[r1,#0]
;;;581
;;;582 /* Reset LSEBYP bit */
;;;583 *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF;
00015e f801f801 STRB r2,[r1],#-0x20
;;;584
;;;585 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
;;;586 switch(RCC_LSE)
000162 2801 CMP r0,#1
000164 d005 BEQ |L1.370|
000166 2804 CMP r0,#4
000168 d102 BNE |L1.368|
;;;587 {
;;;588 case RCC_LSE_ON:
;;;589 /* Set LSEON bit */
;;;590 *(vu8 *) BDCR_ADDRESS = RCC_LSE_ON;
;;;591 break;
;;;592
;;;593 case RCC_LSE_Bypass:
;;;594 /* Set LSEBYP and LSEON bits */
;;;595 *(vu8 *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
00016a 2005 MOVS r0,#5
00016c f881f881 STRB r0,[r1,#0x20]
|L1.368|
;;;596 break;
;;;597
;;;598 default:
;;;599 break;
;;;600 }
;;;601 }
000170 4770 BX lr
|L1.370|
000172 2001 MOVS r0,#1 ;590
000174 f881f881 STRB r0,[r1,#0x20] ;590
000178 4770 BX lr
;;;602
ENDP
RCC_LSICmd PROC
;;;616
;;;617 *(vu32 *) CSR_LSION_BB = (u32)NewState;
00017a 4956 LDR r1,|L1.724|
00017c 6008 STR r0,[r1,#0]
;;;618 }
00017e 4770 BX lr
;;;619
ENDP
RCC_RTCCLKConfig PROC
;;;639 /* Select the RTC clock source */
;;;640 RCC->BDCR |= RCC_RTCCLKSource;
000180 4a4f LDR r2,|L1.704|
000182 6a11 LDR r1,[r2,#0x20]
000184 4301 ORRS r1,r1,r0
000186 6211 STR r1,[r2,#0x20]
;;;641 }
000188 4770 BX lr
;;;642
ENDP
RCC_RTCCLKCmd PROC
;;;657
;;;658 *(vu32 *) BDCR_RTCEN_BB = (u32)NewState;
00018a 4952 LDR r1,|L1.724|
00018c 3944 SUBS r1,r1,#0x44
00018e 6008 STR r0,[r1,#0]
;;;659 }
000190 4770 BX lr
;;;660
ENDP
RCC_GetClocksFreq PROC
;;;669 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
;;;670 {
000192 b530 PUSH {r4,r5,lr}
;;;671 u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
;;;672
;;;673 /* Get SYSCLK source -------------------------------------------------------*/
;;;674 tmp = RCC->CFGR & CFGR_SWS_Mask;
000194 4a4a LDR r2,|L1.704|
000196 6851 LDR r1,[r2,#4]
000198 f001f001 AND r1,r1,#0xc
;;;675
;;;676 switch (tmp)
00019c 4b4e LDR r3,|L1.728|
00019e b189 CBZ r1,|L1.452|
0001a0 2904 CMP r1,#4
0001a2 d011 BEQ |L1.456|
0001a4 2908 CMP r1,#8
0001a6 d11a BNE |L1.478|
;;;677 {
;;;678 case 0x00: /* HSI used as system clock */
;;;679 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
;;;680 break;
;;;681
;;;682 case 0x04: /* HSE used as system clock */
;;;683 RCC_Clocks->SYSCLK_Frequency = HSE_Value;
;;;684 break;
;;;685
;;;686 case 0x08: /* PLL used as system clock */
;;;687 /* Get PLL clock source and multiplication factor ----------------------*/
;;;688 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
0001a8 6851 LDR r1,[r2,#4]
0001aa f401f401 AND r1,r1,#0x3c0000
;;;689 pllmull = ( pllmull >> 18) + 2;
0001ae 2402 MOVS r4,#2
0001b0 eb04eb04 ADD r1,r4,r1,LSR #18
;;;690
;;;691 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
0001b4 6854 LDR r4,[r2,#4]
0001b6 f404f404 AND r4,r4,#0x10000
;;;692
;;;693 if (pllsource == 0x00)
0001ba 4d48 LDR r5,|L1.732|
0001bc b934 CBNZ r4,|L1.460|
;;;694 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
;;;695 RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
0001be 4369 MULS r1,r5,r1
0001c0 6001 STR r1,[r0,#0]
0001c2 e00d B |L1.480|
|L1.452|
0001c4 6003 STR r3,[r0,#0] ;679
0001c6 e00b B |L1.480|
|L1.456|
0001c8 6003 STR r3,[r0,#0] ;683
0001ca e009 B |L1.480|
|L1.460|
;;;696 }
;;;697 else
;;;698 {/* HSE selected as PLL clock entry */
;;;699
;;;700 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
0001cc 6854 LDR r4,[r2,#4]
0001ce 03a4 LSLS r4,r4,#14
0001d0 d502 BPL |L1.472|
;;;701 {/* HSE oscillator clock divided by 2 */
;;;702
;;;703 RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
0001d2 4369 MULS r1,r5,r1
0001d4 6001 STR r1,[r0,#0]
0001d6 e003 B |L1.480|
|L1.472|
;;;704 }
;;;705 else
;;;706 {
;;;707 RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
0001d8 4359 MULS r1,r3,r1
0001da 6001 STR r1,[r0,#0]
0001dc e000 B |L1.480|
|L1.478|
;;;708 }
;;;709 }
;;;710 break;
;;;711
;;;712 default:
;;;713 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
0001de 6003 STR r3,[r0,#0]
|L1.480|
;;;714 break;
;;;715 }
;;;716
;;;717 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
;;;718 /* Get HCLK prescaler */
;;;719 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
0001e0 6851 LDR r1,[r2,#4]
0001e2 f001f001 AND r1,r1,#0xf0
;;;720 tmp = tmp >> 4;
0001e6 0909 LSRS r1,r1,#4
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