📄 stm32f10x_rcc.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 919] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\output\stm32f10x_rcc.o --depend=.\output\stm32f10x_rcc.d --device=DARMSTM --apcs=interwork -O1 -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -IC:\Keil\ARM\INC\ST\STM32F10x --omf_browse=.\output\stm32f10x_rcc.crf ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_rcc.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
RCC_DeInit PROC
;;;129 /* Set HSION bit */
;;;130 RCC->CR |= (u32)0x00000001;
000000 48af LDR r0,|L1.704|
000002 6801 LDR r1,[r0,#0]
000004 f041f041 ORR r1,r1,#1
000008 6001 STR r1,[r0,#0]
;;;131
;;;132 /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */
;;;133 RCC->CFGR &= (u32)0xF8FF0000;
00000a 6841 LDR r1,[r0,#4]
00000c 4aad LDR r2,|L1.708|
00000e 4011 ANDS r1,r1,r2
000010 6041 STR r1,[r0,#4]
;;;134
;;;135 /* Reset HSEON, CSSON and PLLON bits */
;;;136 RCC->CR &= (u32)0xFEF6FFFF;
000012 6801 LDR r1,[r0,#0]
000014 4aac LDR r2,|L1.712|
000016 4011 ANDS r1,r1,r2
000018 6001 STR r1,[r0,#0]
;;;137
;;;138 /* Reset HSEBYP bit */
;;;139 RCC->CR &= (u32)0xFFFBFFFF;
00001a 6801 LDR r1,[r0,#0]
00001c f421f421 BIC r1,r1,#0x40000
000020 6001 STR r1,[r0,#0]
;;;140
;;;141 /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
;;;142 RCC->CFGR &= (u32)0xFF80FFFF;
000022 6841 LDR r1,[r0,#4]
000024 f421f421 BIC r1,r1,#0x7f0000
000028 6041 STR r1,[r0,#4]
;;;143
;;;144 /* Disable all interrupts */
;;;145 RCC->CIR = 0x00000000;
00002a 2100 MOVS r1,#0
00002c 6081 STR r1,[r0,#8]
;;;146 }
00002e 4770 BX lr
;;;147
ENDP
RCC_HSEConfig PROC
;;;168 /* Reset HSEON bit */
;;;169 RCC->CR &= CR_HSEON_Reset;
000030 49a3 LDR r1,|L1.704|
000032 680a LDR r2,[r1,#0]
000034 f422f422 BIC r2,r2,#0x10000
000038 600a STR r2,[r1,#0]
;;;170
;;;171 /* Reset HSEBYP bit */
;;;172 RCC->CR &= CR_HSEBYP_Reset;
00003a 680a LDR r2,[r1,#0]
00003c f422f422 BIC r2,r2,#0x40000
000040 600a STR r2,[r1,#0]
;;;173
;;;174 /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
;;;175 switch(RCC_HSE)
000042 f5b0f5b0 CMP r0,#0x10000
000046 d007 BEQ |L1.88|
000048 f5b0f5b0 CMP r0,#0x40000
00004c d103 BNE |L1.86|
;;;176 {
;;;177 case RCC_HSE_ON:
;;;178 /* Set HSEON bit */
;;;179 RCC->CR |= CR_HSEON_Set;
;;;180 break;
;;;181
;;;182 case RCC_HSE_Bypass:
;;;183 /* Set HSEBYP and HSEON bits */
;;;184 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
00004e 6808 LDR r0,[r1,#0]
000050 f440f440 ORR r0,r0,#0x50000
000054 6008 STR r0,[r1,#0]
|L1.86|
;;;185 break;
;;;186
;;;187 default:
;;;188 break;
;;;189 }
;;;190 }
000056 4770 BX lr
|L1.88|
000058 6808 LDR r0,[r1,#0] ;179
00005a f440f440 ORR r0,r0,#0x10000 ;179
00005e 6008 STR r0,[r1,#0] ;179
000060 4770 BX lr
;;;191
ENDP
RCC_GetFlagStatus PROC
;;;990 FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG)
;;;991 {
000062 4603 MOV r3,r0
;;;992 u32 tmp = 0;
;;;993 u32 statusreg = 0;
;;;994 FlagStatus bitstatus = RESET;
000064 2000 MOVS r0,#0
;;;995
;;;996 /* Check the parameters */
;;;997 assert_param(IS_RCC_FLAG(RCC_FLAG));
;;;998
;;;999 /* Get the RCC register index */
;;;1000 tmp = RCC_FLAG >> 5;
000066 0959 LSRS r1,r3,#5
;;;1001
;;;1002 if (tmp == 1) /* The flag to check is in CR register */
000068 4a95 LDR r2,|L1.704|
00006a 2901 CMP r1,#1
00006c d101 BNE |L1.114|
;;;1003 {
;;;1004 statusreg = RCC->CR;
00006e 6811 LDR r1,[r2,#0]
000070 e004 B |L1.124|
|L1.114|
;;;1005 }
;;;1006 else if (tmp == 2) /* The flag to check is in BDCR register */
000072 2902 CMP r1,#2
000074 d101 BNE |L1.122|
;;;1007 {
;;;1008 statusreg = RCC->BDCR;
000076 6a11 LDR r1,[r2,#0x20]
000078 e000 B |L1.124|
|L1.122|
;;;1009 }
;;;1010 else /* The flag to check is in CSR register */
;;;1011 {
;;;1012 statusreg = RCC->CSR;
00007a 6a51 LDR r1,[r2,#0x24]
|L1.124|
;;;1013 }
;;;1014
;;;1015 /* Get the flag position */
;;;1016 tmp = RCC_FLAG & FLAG_Mask;
00007c f003f003 AND r2,r3,#0x1f
;;;1017
;;;1018 if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)
000080 2301 MOVS r3,#1
000082 4093 LSLS r3,r3,r2
000084 420b TST r3,r1
000086 d000 BEQ |L1.138|
;;;1019 {
;;;1020 bitstatus = SET;
000088 2001 MOVS r0,#1
|L1.138|
;;;1021 }
;;;1022 else
;;;1023 {
;;;1024 bitstatus = RESET;
;;;1025 }
;;;1026
;;;1027 /* Return the flag status */
;;;1028 return bitstatus;
;;;1029 }
00008a 4770 BX lr
;;;1030
ENDP
RCC_WaitForHSEStartUp PROC
;;;201 ErrorStatus RCC_WaitForHSEStartUp(void)
;;;202 {
00008c b530 PUSH {r4,r5,lr}
00008e 4c8f LDR r4,|L1.716|
000090 f240f240 MOV r5,#0x1ff
|L1.148|
;;;203 ErrorStatus status = ERROR;
;;;204
;;;205 /* Wait till HSE is ready and if Time out is reached exit */
;;;206 do
;;;207 {
;;;208 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
000094 2031 MOVS r0,#0x31
000096 f7fff7ff BL RCC_GetFlagStatus
00009a 7020 STRB r0,[r4,#0] ; HSEStatus
;;;209 StartUpCounter++;
00009c 6860 LDR r0,[r4,#4] ; StartUpCounter
00009e 1c40 ADDS r0,r0,#1
0000a0 6060 STR r0,[r4,#4] ; StartUpCounter
;;;210 } while((HSEStatus == RESET) && (StartUpCounter != HSEStartUp_TimeOut));
0000a2 7820 LDRB r0,[r4,#0] ; HSEStatus
0000a4 b910 CBNZ r0,|L1.172|
0000a6 6860 LDR r0,[r4,#4] ; StartUpCounter
0000a8 42a8 CMP r0,r5
0000aa d1f3 BNE |L1.148|
|L1.172|
;;;211
;;;212
;;;213 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
0000ac 2031 MOVS r0,#0x31
0000ae f7fff7ff BL RCC_GetFlagStatus
0000b2 b108 CBZ r0,|L1.184|
;;;214 {
;;;215 status = SUCCESS;
0000b4 2001 MOVS r0,#1
;;;216 }
;;;217 else
;;;218 {
;;;219 status = ERROR;
;;;220 }
;;;221
;;;222 return (status);
;;;223 }
0000b6 bd30 POP {r4,r5,pc}
|L1.184|
0000b8 2000 MOVS r0,#0 ;219
0000ba bd30 POP {r4,r5,pc}
;;;224
ENDP
RCC_AdjustHSICalibrationValue PROC
;;;240
;;;241 tmpreg = RCC->CR;
0000bc 4a80 LDR r2,|L1.704|
0000be 6811 LDR r1,[r2,#0]
;;;242
;;;243 /* Clear HSITRIM[4:0] bits */
;;;244 tmpreg &= CR_HSITRIM_Mask;
0000c0 f021f021 BIC r1,r1,#0xf8
;;;245
;;;246 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
;;;247 tmpreg |= (u32)HSICalibrationValue << 3;
0000c4 ea41ea41 ORR r0,r1,r0,LSL #3
;;;248
;;;249 /* Store the new value */
;;;250 RCC->CR = tmpreg;
0000c8 6010 STR r0,[r2,#0]
;;;251 }
0000ca 4770 BX lr
;;;252
ENDP
RCC_HSICmd PROC
;;;267
;;;268 *(vu32 *) CR_HSION_BB = (u32)NewState;
0000cc 4980 LDR r1,|L1.720|
0000ce 6008 STR r0,[r1,#0]
;;;269 }
0000d0 4770 BX lr
;;;270
ENDP
RCC_PLLConfig PROC
;;;295
;;;296 tmpreg = RCC->CFGR;
0000d2 4b7b LDR r3,|L1.704|
0000d4 685a LDR r2,[r3,#4]
;;;297
;;;298 /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
;;;299 tmpreg &= CFGR_PLL_Mask;
0000d6 f422f422 BIC r2,r2,#0x3f0000
;;;300
;;;301 /* Set the PLL configuration bits */
;;;302 tmpreg |= RCC_PLLSource | RCC_PLLMul;
0000da 4308 ORRS r0,r0,r1
0000dc 4310 ORRS r0,r0,r2
;;;303
;;;304 /* Store the new value */
;;;305 RCC->CFGR = tmpreg;
0000de 6058 STR r0,[r3,#4]
;;;306 }
0000e0 4770 BX lr
;;;307
ENDP
RCC_PLLCmd PROC
;;;321
;;;322 *(vu32 *) CR_PLLON_BB = (u32)NewState;
0000e2 497b LDR r1,|L1.720|
0000e4 6608 STR r0,[r1,#0x60]
;;;323 }
0000e6 4770 BX lr
;;;324
ENDP
RCC_SYSCLKConfig PROC
;;;342
;;;343 tmpreg = RCC->CFGR;
0000e8 4a75 LDR r2,|L1.704|
0000ea 6851 LDR r1,[r2,#4]
;;;344
;;;345 /* Clear SW[1:0] bits */
;;;346 tmpreg &= CFGR_SW_Mask;
0000ec f021f021 BIC r1,r1,#3
;;;347
;;;348 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
;;;349 tmpreg |= RCC_SYSCLKSource;
0000f0 4301 ORRS r1,r1,r0
;;;350
;;;351 /* Store the new value */
;;;352 RCC->CFGR = tmpreg;
0000f2 6051 STR r1,[r2,#4]
;;;353 }
0000f4 4770 BX lr
;;;354
ENDP
RCC_GetSYSCLKSource PROC
;;;367 {
;;;368 return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
0000f6 4872 LDR r0,|L1.704|
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