📄 stm32f10x_spi.txt
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0001f0 430a ORRS r2,r2,r1
0001f2 8002 STRH r2,[r0,#0]
;;;575 }
0001f4 4770 BX lr
;;;576
ENDP
SPI_TransmitCRC PROC
;;;589 /* Enable the selected SPI CRC transmission */
;;;590 SPIx->CR1 |= CR1_CRCNext_Set;
0001f6 8801 LDRH r1,[r0,#0]
0001f8 f441f441 ORR r1,r1,#0x1000
0001fc 8001 STRH r1,[r0,#0]
;;;591 }
0001fe 4770 BX lr
;;;592
ENDP
SPI_CalculateCRC PROC
;;;608
;;;609 if (NewState != DISABLE)
000200 b121 CBZ r1,|L1.524|
;;;610 {
;;;611 /* Enable the selected SPI CRC calculation */
;;;612 SPIx->CR1 |= CR1_CRCEN_Set;
000202 8801 LDRH r1,[r0,#0]
000204 f441f441 ORR r1,r1,#0x2000
000208 8001 STRH r1,[r0,#0]
;;;613 }
;;;614 else
;;;615 {
;;;616 /* Disable the selected SPI CRC calculation */
;;;617 SPIx->CR1 &= CR1_CRCEN_Reset;
;;;618 }
;;;619 }
00020a 4770 BX lr
|L1.524|
00020c 8801 LDRH r1,[r0,#0] ;617
00020e f421f421 BIC r1,r1,#0x2000 ;617
000212 8001 STRH r1,[r0,#0] ;617
000214 4770 BX lr
;;;620
ENDP
SPI_GetCRC PROC
;;;640
;;;641 if (SPI_CRC != SPI_CRC_Rx)
000216 2901 CMP r1,#1
000218 d001 BEQ |L1.542|
;;;642 {
;;;643 /* Get the Tx CRC register */
;;;644 crcreg = SPIx->TXCRCR;
00021a 8b00 LDRH r0,[r0,#0x18]
;;;645 }
;;;646 else
;;;647 {
;;;648 /* Get the Rx CRC register */
;;;649 crcreg = SPIx->RXCRCR;
;;;650 }
;;;651
;;;652 /* Return the selected CRC register */
;;;653 return crcreg;
;;;654 }
00021c 4770 BX lr
|L1.542|
00021e 8a80 LDRH r0,[r0,#0x14] ;649
000220 4770 BX lr
;;;655
ENDP
SPI_GetCRCPolynomial PROC
;;;668 /* Return the CRC polynomial register */
;;;669 return SPIx->CRCPR;
000222 8a00 LDRH r0,[r0,#0x10]
;;;670 }
000224 4770 BX lr
;;;671
ENDP
SPI_BiDirectionalLineConfig PROC
;;;690
;;;691 if (SPI_Direction == SPI_Direction_Tx)
000226 f5b1f5b1 CMP r1,#0x4000
00022a d104 BNE |L1.566|
;;;692 {
;;;693 /* Set the Tx only mode */
;;;694 SPIx->CR1 |= SPI_Direction_Tx;
00022c 8801 LDRH r1,[r0,#0]
00022e f441f441 ORR r1,r1,#0x4000
000232 8001 STRH r1,[r0,#0]
;;;695 }
;;;696 else
;;;697 {
;;;698 /* Set the Rx only mode */
;;;699 SPIx->CR1 &= SPI_Direction_Rx;
;;;700 }
;;;701 }
000234 4770 BX lr
|L1.566|
000236 8801 LDRH r1,[r0,#0] ;699
000238 f421f421 BIC r1,r1,#0x4000 ;699
00023c 8001 STRH r1,[r0,#0] ;699
00023e 4770 BX lr
;;;702
ENDP
SPI_I2S_GetFlagStatus PROC
;;;722 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, u16 SPI_I2S_FLAG)
;;;723 {
000240 4602 MOV r2,r0
;;;724 FlagStatus bitstatus = RESET;
000242 2000 MOVS r0,#0
;;;725
;;;726 /* Check the parameters */
;;;727 assert_param(IS_SPI_ALL_PERIPH(SPIx));
;;;728 assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
;;;729
;;;730 /* Check the status of the specified SPI/I2S flag */
;;;731 if ((SPIx->SR & SPI_I2S_FLAG) != (u16)RESET)
000244 8912 LDRH r2,[r2,#8]
000246 420a TST r2,r1
000248 d000 BEQ |L1.588|
;;;732 {
;;;733 /* SPI_I2S_FLAG is set */
;;;734 bitstatus = SET;
00024a 2001 MOVS r0,#1
|L1.588|
;;;735 }
;;;736 else
;;;737 {
;;;738 /* SPI_I2S_FLAG is reset */
;;;739 bitstatus = RESET;
;;;740 }
;;;741 /* Return the SPI_I2S_FLAG status */
;;;742 return bitstatus;
;;;743 }
00024c 4770 BX lr
;;;744
ENDP
SPI_I2S_ClearFlag PROC
;;;768 /* SPI_FLAG_MODF flag clear */
;;;769 if(SPI_I2S_FLAG == SPI_FLAG_MODF)
00024e 2920 CMP r1,#0x20
000250 d105 BNE |L1.606|
;;;770 {
;;;771 /* Read SR register */
;;;772 (void)SPIx->SR;
000252 8901 LDRH r1,[r0,#8]
;;;773
;;;774 /* Write on CR1 register */
;;;775 SPIx->CR1 |= CR1_SPE_Set;
000254 8801 LDRH r1,[r0,#0]
000256 f041f041 ORR r1,r1,#0x40
00025a 8001 STRH r1,[r0,#0]
;;;776 }
;;;777 /* SPI_I2S_FLAG_OVR flag or I2S_FLAG_UDR flag clear */
;;;778 else if ((SPI_I2S_FLAG == SPI_I2S_FLAG_OVR) || (SPI_I2S_FLAG == I2S_FLAG_UDR))
;;;779 {
;;;780 /* Read SR register (Before clearing OVR flag, it is mandatory to read
;;;781 SPI_I2S_DR register)*/
;;;782 (void)SPIx->SR;
;;;783 }
;;;784 else /* SPI_FLAG_CRCERR flag clear */
;;;785 {
;;;786 /* Clear the selected SPI flag */
;;;787 SPIx->SR = (u16)~SPI_I2S_FLAG;
;;;788 }
;;;789 }
00025c 4770 BX lr
|L1.606|
00025e 2940 CMP r1,#0x40 ;778
000260 d001 BEQ |L1.614|
000262 2908 CMP r1,#8 ;778
000264 d101 BNE |L1.618|
|L1.614|
000266 8900 LDRH r0,[r0,#8] ;782
000268 4770 BX lr
|L1.618|
00026a 43c9 MVNS r1,r1 ;787
00026c 8101 STRH r1,[r0,#8] ;787
00026e 4770 BX lr
;;;790
ENDP
SPI_I2S_GetITStatus PROC
;;;808 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, u8 SPI_I2S_IT)
;;;809 {
000270 b530 PUSH {r4,r5,lr}
000272 4602 MOV r2,r0
;;;810 ITStatus bitstatus = RESET;
000274 2000 MOVS r0,#0
;;;811 u16 itpos = 0, itmask = 0, enablestatus = 0;
;;;812
;;;813 /* Check the parameters */
;;;814 assert_param(IS_SPI_ALL_PERIPH(SPIx));
;;;815 assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
;;;816
;;;817 /* Get the SPI/I2S IT index */
;;;818 itpos = (u16)((u16)0x01 << (SPI_I2S_IT & (u8)0x0F));
000276 f001f001 AND r5,r1,#0xf
00027a 2401 MOVS r4,#1
00027c fa04fa04 LSL r3,r4,r5
000280 b29b UXTH r3,r3
;;;819
;;;820 /* Get the SPI/I2S IT mask */
;;;821 itmask = SPI_I2S_IT >> 4;
000282 0909 LSRS r1,r1,#4
;;;822 /* Set the IT mask */
;;;823 itmask = (u16)((u16)0x01 << itmask);
000284 408c LSLS r4,r4,r1
000286 b2a4 UXTH r4,r4
;;;824 /* Get the SPI_I2S_IT enable bit status */
;;;825 enablestatus = (SPIx->CR2 & itmask) ;
000288 8891 LDRH r1,[r2,#4]
00028a 4021 ANDS r1,r1,r4
;;;826
;;;827 /* Check the status of the specified SPI/I2S interrupt */
;;;828 if (((SPIx->SR & itpos) != (u16)RESET) && enablestatus)
00028c 8912 LDRH r2,[r2,#8]
00028e 421a TST r2,r3
000290 d002 BEQ |L1.664|
000292 2900 CMP r1,#0
000294 d000 BEQ |L1.664|
;;;829 {
;;;830 /* SPI_I2S_IT is set */
;;;831 bitstatus = SET;
000296 2001 MOVS r0,#1
|L1.664|
;;;832 }
;;;833 else
;;;834 {
;;;835 /* SPI_I2S_IT is reset */
;;;836 bitstatus = RESET;
;;;837 }
;;;838 /* Return the SPI_I2S_IT status */
;;;839 return bitstatus;
;;;840 }
000298 bd30 POP {r4,r5,pc}
;;;841
ENDP
SPI_I2S_ClearITPendingBit PROC
;;;865 /* SPI_IT_MODF pending bit clear */
;;;866 if(SPI_I2S_IT == SPI_IT_MODF)
00029a 2955 CMP r1,#0x55
00029c d105 BNE |L1.682|
;;;867 {
;;;868 /* Read SR register */
;;;869 (void)SPIx->SR;
00029e 8901 LDRH r1,[r0,#8]
;;;870 /* Write on CR1 register */
;;;871 SPIx->CR1 |= CR1_SPE_Set;
0002a0 8801 LDRH r1,[r0,#0]
0002a2 f041f041 ORR r1,r1,#0x40
0002a6 8001 STRH r1,[r0,#0]
;;;872 }
;;;873 /* SPI_I2S_IT_OVR or I2S_IT_UDR pending bit clear */
;;;874 else if((SPI_I2S_IT == SPI_I2S_IT_OVR) || (SPI_I2S_IT == I2S_IT_UDR))
;;;875 {
;;;876 /* Read SR register */
;;;877 (void)(SPIx->SR);
;;;878 }
;;;879 else /* SPI_IT_CRCERR pending bit clear */
;;;880 {
;;;881 /* Get the SPI/I2S IT index */
;;;882 itpos = (u16)((u16)0x01 << (SPI_I2S_IT & (u8)0x0F));
;;;883 /* Clear the selected SPI/I2S interrupt pending bits */
;;;884 SPIx->SR = (u16)~itpos;
;;;885 }
;;;886 }
0002a8 4770 BX lr
|L1.682|
0002aa 2956 CMP r1,#0x56 ;874
0002ac d001 BEQ |L1.690|
0002ae 2953 CMP r1,#0x53 ;874
0002b0 d101 BNE |L1.694|
|L1.690|
0002b2 8900 LDRH r0,[r0,#8] ;877
0002b4 4770 BX lr
|L1.694|
0002b6 f001f001 AND r2,r1,#0xf ;882
0002ba 2101 MOVS r1,#1 ;882
0002bc 4091 LSLS r1,r1,r2 ;882
0002be 43c9 MVNS r1,r1 ;884
0002c0 8101 STRH r1,[r0,#8] ;884
0002c2 4770 BX lr
;;;887
ENDP
|L1.708|
0002c4 bfffc800 DCD 0xbfffc800
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