📄 stm32f10x_spi.txt
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00010a 4308 ORRS r0,r0,r1
00010c 4302 ORRS r2,r2,r0
00010e 842a STRH r2,[r5,#0x20]
;;;248
;;;249 /* Configure the I2S with the SPI_InitStruct values */
;;;250 tmpreg |= (u16)(I2S_Mode_Select | I2S_InitStruct->I2S_Mode | \
000110 8821 LDRH r1,[r4,#0]
000112 8860 LDRH r0,[r4,#2]
000114 8962 LDRH r2,[r4,#0xa]
000116 4301 ORRS r1,r1,r0
000118 88a0 LDRH r0,[r4,#4]
00011a 4310 ORRS r0,r0,r2
00011c 4301 ORRS r1,r1,r0
00011e 4339 ORRS r1,r1,r7
000120 f441f441 ORR r0,r1,#0x800
;;;251 I2S_InitStruct->I2S_Standard | I2S_InitStruct->I2S_DataFormat | \
;;;252 I2S_InitStruct->I2S_CPOL);
;;;253
;;;254 /* Write to SPIx I2SCFGR */
;;;255 SPIx->I2SCFGR = tmpreg;
000124 83a8 STRH r0,[r5,#0x1c]
;;;256 }
000126 b005 ADD sp,sp,#0x14
000128 bdf0 POP {r4-r7,pc}
;;;257
ENDP
SPI_StructInit PROC
;;;269 /* Initialize the SPI_Direction member */
;;;270 SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
00012a 2100 MOVS r1,#0
00012c 8001 STRH r1,[r0,#0]
;;;271
;;;272 /* initialize the SPI_Mode member */
;;;273 SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
00012e 8041 STRH r1,[r0,#2]
;;;274
;;;275 /* initialize the SPI_DataSize member */
;;;276 SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
000130 8081 STRH r1,[r0,#4]
;;;277
;;;278 /* Initialize the SPI_CPOL member */
;;;279 SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
000132 80c1 STRH r1,[r0,#6]
;;;280
;;;281 /* Initialize the SPI_CPHA member */
;;;282 SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
000134 8101 STRH r1,[r0,#8]
;;;283
;;;284 /* Initialize the SPI_NSS member */
;;;285 SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
000136 8141 STRH r1,[r0,#0xa]
;;;286
;;;287 /* Initialize the SPI_BaudRatePrescaler member */
;;;288 SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
000138 8181 STRH r1,[r0,#0xc]
;;;289
;;;290 /* Initialize the SPI_FirstBit member */
;;;291 SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
00013a 81c1 STRH r1,[r0,#0xe]
;;;292
;;;293 /* Initialize the SPI_CRCPolynomial member */
;;;294 SPI_InitStruct->SPI_CRCPolynomial = 7;
00013c 2107 MOVS r1,#7
00013e 8201 STRH r1,[r0,#0x10]
;;;295 }
000140 4770 BX lr
;;;296
ENDP
I2S_StructInit PROC
;;;308 /* Initialize the I2S_Mode member */
;;;309 I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
000142 2100 MOVS r1,#0
000144 8001 STRH r1,[r0,#0]
;;;310
;;;311 /* Initialize the I2S_Standard member */
;;;312 I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
000146 8041 STRH r1,[r0,#2]
;;;313
;;;314 /* Initialize the I2S_DataFormat member */
;;;315 I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
000148 8081 STRH r1,[r0,#4]
;;;316
;;;317 /* Initialize the I2S_MCLKOutput member */
;;;318 I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
00014a 80c1 STRH r1,[r0,#6]
;;;319
;;;320 /* Initialize the I2S_AudioFreq member */
;;;321 I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
00014c 2202 MOVS r2,#2
00014e 8102 STRH r2,[r0,#8]
;;;322
;;;323 /* Initialize the I2S_CPOL member */
;;;324 I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
000150 8141 STRH r1,[r0,#0xa]
;;;325 }
000152 4770 BX lr
;;;326
ENDP
SPI_Cmd PROC
;;;341
;;;342 if (NewState != DISABLE)
000154 b121 CBZ r1,|L1.352|
;;;343 {
;;;344 /* Enable the selected SPI peripheral */
;;;345 SPIx->CR1 |= CR1_SPE_Set;
000156 8801 LDRH r1,[r0,#0]
000158 f041f041 ORR r1,r1,#0x40
00015c 8001 STRH r1,[r0,#0]
;;;346 }
;;;347 else
;;;348 {
;;;349 /* Disable the selected SPI peripheral */
;;;350 SPIx->CR1 &= CR1_SPE_Reset;
;;;351 }
;;;352 }
00015e 4770 BX lr
|L1.352|
000160 8801 LDRH r1,[r0,#0] ;350
000162 f021f021 BIC r1,r1,#0x40 ;350
000166 8001 STRH r1,[r0,#0] ;350
000168 4770 BX lr
;;;353
ENDP
I2S_Cmd PROC
;;;368
;;;369 if (NewState != DISABLE)
00016a b121 CBZ r1,|L1.374|
;;;370 {
;;;371 /* Enable the selected SPI peripheral (in I2S mode) */
;;;372 SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
00016c 8b81 LDRH r1,[r0,#0x1c]
00016e f441f441 ORR r1,r1,#0x400
000172 8381 STRH r1,[r0,#0x1c]
;;;373 }
;;;374 else
;;;375 {
;;;376 /* Disable the selected SPI peripheral (in I2S mode) */
;;;377 SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
;;;378 }
;;;379 }
000174 4770 BX lr
|L1.374|
000176 8b81 LDRH r1,[r0,#0x1c] ;377
000178 f421f421 BIC r1,r1,#0x400 ;377
00017c 8381 STRH r1,[r0,#0x1c] ;377
00017e 4770 BX lr
;;;380
ENDP
SPI_I2S_ITConfig PROC
;;;407 /* Get the SPI/I2S IT index */
;;;408 itpos = SPI_I2S_IT >> 4;
000180 0909 LSRS r1,r1,#4
;;;409 /* Set the IT mask */
;;;410 itmask = (u16)((u16)1 << itpos);
000182 2301 MOVS r3,#1
000184 408b LSLS r3,r3,r1
000186 b299 UXTH r1,r3
;;;411
;;;412 if (NewState != DISABLE)
000188 b11a CBZ r2,|L1.402|
;;;413 {
;;;414 /* Enable the selected SPI/I2S interrupt */
;;;415 SPIx->CR2 |= itmask;
00018a 8882 LDRH r2,[r0,#4]
00018c 430a ORRS r2,r2,r1
00018e 8082 STRH r2,[r0,#4]
;;;416 }
;;;417 else
;;;418 {
;;;419 /* Disable the selected SPI/I2S interrupt */
;;;420 SPIx->CR2 &= (u16)~itmask;
;;;421 }
;;;422 }
000190 4770 BX lr
|L1.402|
000192 8882 LDRH r2,[r0,#4] ;420
000194 438a BICS r2,r2,r1 ;420
000196 8082 STRH r2,[r0,#4] ;420
000198 4770 BX lr
;;;423
ENDP
SPI_I2S_DMACmd PROC
;;;447
;;;448 if (NewState != DISABLE)
00019a b11a CBZ r2,|L1.420|
;;;449 {
;;;450 /* Enable the selected SPI/I2S DMA requests */
;;;451 SPIx->CR2 |= SPI_I2S_DMAReq;
00019c 8882 LDRH r2,[r0,#4]
00019e 430a ORRS r2,r2,r1
0001a0 8082 STRH r2,[r0,#4]
;;;452 }
;;;453 else
;;;454 {
;;;455 /* Disable the selected SPI/I2S DMA requests */
;;;456 SPIx->CR2 &= (u16)~SPI_I2S_DMAReq;
;;;457 }
;;;458 }
0001a2 4770 BX lr
|L1.420|
0001a4 8882 LDRH r2,[r0,#4] ;456
0001a6 438a BICS r2,r2,r1 ;456
0001a8 8082 STRH r2,[r0,#4] ;456
0001aa 4770 BX lr
;;;459
ENDP
SPI_I2S_SendData PROC
;;;475 /* Write in the DR register the data to be sent */
;;;476 SPIx->DR = Data;
0001ac 8181 STRH r1,[r0,#0xc]
;;;477 }
0001ae 4770 BX lr
;;;478
ENDP
SPI_I2S_ReceiveData PROC
;;;493 /* Return the data in the DR register */
;;;494 return SPIx->DR;
0001b0 8980 LDRH r0,[r0,#0xc]
;;;495 }
0001b2 4770 BX lr
;;;496
ENDP
SPI_NSSInternalSoftwareConfig PROC
;;;514
;;;515 if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
0001b4 f5a1f5a1 SUB r2,r1,#0xfe00
0001b8 3aff SUBS r2,r2,#0xff
0001ba d004 BEQ |L1.454|
;;;516 {
;;;517 /* Set NSS pin internally by software */
;;;518 SPIx->CR1 |= SPI_NSSInternalSoft_Set;
0001bc 8801 LDRH r1,[r0,#0]
0001be f441f441 ORR r1,r1,#0x100
0001c2 8001 STRH r1,[r0,#0]
;;;519 }
;;;520 else
;;;521 {
;;;522 /* Reset NSS pin internally by software */
;;;523 SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
;;;524 }
;;;525 }
0001c4 4770 BX lr
|L1.454|
0001c6 8801 LDRH r1,[r0,#0] ;523
0001c8 f421f421 BIC r1,r1,#0x100 ;523
0001cc 8001 STRH r1,[r0,#0] ;523
0001ce 4770 BX lr
;;;526
ENDP
SPI_SSOutputCmd PROC
;;;541
;;;542 if (NewState != DISABLE)
0001d0 b121 CBZ r1,|L1.476|
;;;543 {
;;;544 /* Enable the selected SPI SS output */
;;;545 SPIx->CR2 |= CR2_SSOE_Set;
0001d2 8881 LDRH r1,[r0,#4]
0001d4 f041f041 ORR r1,r1,#4
0001d8 8081 STRH r1,[r0,#4]
;;;546 }
;;;547 else
;;;548 {
;;;549 /* Disable the selected SPI SS output */
;;;550 SPIx->CR2 &= CR2_SSOE_Reset;
;;;551 }
;;;552 }
0001da 4770 BX lr
|L1.476|
0001dc 8881 LDRH r1,[r0,#4] ;550
0001de f021f021 BIC r1,r1,#4 ;550
0001e2 8081 STRH r1,[r0,#4] ;550
0001e4 4770 BX lr
;;;553
ENDP
SPI_DataSizeConfig PROC
;;;571 /* Clear DFF bit */
;;;572 SPIx->CR1 &= (u16)~SPI_DataSize_16b;
0001e6 8802 LDRH r2,[r0,#0]
0001e8 f422f422 BIC r2,r2,#0x800
0001ec 8002 STRH r2,[r0,#0]
;;;573 /* Set new DFF bit value */
;;;574 SPIx->CR1 |= SPI_DataSize;
0001ee 8802 LDRH r2,[r0,#0]
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