📄 stm32f10x_spi.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 919] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\output\stm32f10x_spi.o --depend=.\output\stm32f10x_spi.d --device=DARMSTM --apcs=interwork -O1 -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -IC:\Keil\ARM\INC\ST\STM32F10x --omf_browse=.\output\stm32f10x_spi.crf ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_spi.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
SPI_I2S_DeInit PROC
;;;64 void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
;;;65 {
000000 b510 PUSH {r4,lr}
;;;66 /* Check the parameters */
;;;67 assert_param(IS_SPI_ALL_PERIPH(SPIx));
;;;68
;;;69 switch (*(u32*)&SPIx)
000002 49b0 LDR r1,|L1.708|
000004 1840 ADDS r0,r0,r1
000006 d010 BEQ |L1.42|
000008 f5b0f5b0 CMP r0,#0x400
00000c d018 BEQ |L1.64|
00000e f5b0f5b0 CMP r0,#0xf800
000012 d120 BNE |L1.86|
;;;70 {
;;;71 case SPI1_BASE:
;;;72 /* Enable SPI1 reset state */
;;;73 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
000014 2101 MOVS r1,#1
000016 030c LSLS r4,r1,#12
000018 4620 MOV r0,r4
00001a f7fff7ff BL RCC_APB2PeriphResetCmd
;;;74 /* Release SPI1 from reset state */
;;;75 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
00001e 4620 MOV r0,r4
000020 e8bde8bd POP {r4,lr}
000024 2100 MOVS r1,#0
000026 f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.42|
;;;76 break;
;;;77
;;;78 case SPI2_BASE:
;;;79 /* Enable SPI2 reset state */
;;;80 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
00002a 2101 MOVS r1,#1
00002c 038c LSLS r4,r1,#14
00002e 4620 MOV r0,r4
000030 f7fff7ff BL RCC_APB1PeriphResetCmd
;;;81 /* Release SPI2 from reset state */
;;;82 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
000034 4620 MOV r0,r4
000036 e8bde8bd POP {r4,lr}
00003a 2100 MOVS r1,#0
00003c f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.64|
;;;83 break;
;;;84
;;;85 case SPI3_BASE:
;;;86 /* Enable SPI3 reset state */
;;;87 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
000040 2101 MOVS r1,#1
000042 03cc LSLS r4,r1,#15
000044 4620 MOV r0,r4
000046 f7fff7ff BL RCC_APB1PeriphResetCmd
;;;88 /* Release SPI3 from reset state */
;;;89 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
00004a 4620 MOV r0,r4
00004c e8bde8bd POP {r4,lr}
000050 2100 MOVS r1,#0
000052 f7fff7ff B.W RCC_APB1PeriphResetCmd
|L1.86|
;;;90 break;
;;;91
;;;92 default:
;;;93 break;
;;;94 }
;;;95 }
000056 bd10 POP {r4,pc}
;;;96
ENDP
SPI_Init PROC
;;;108 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
;;;109 {
000058 b530 PUSH {r4,r5,lr}
;;;110 u16 tmpreg = 0;
;;;111
;;;112 /* check the parameters */
;;;113 assert_param(IS_SPI_ALL_PERIPH(SPIx));
;;;114
;;;115 /* Check the SPI parameters */
;;;116 assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
;;;117 assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
;;;118 assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
;;;119 assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
;;;120 assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
;;;121 assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
;;;122 assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
;;;123 assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
;;;124 assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
;;;125
;;;126 /*---------------------------- SPIx CR1 Configuration ------------------------*/
;;;127 /* Get the SPIx CR1 value */
;;;128 tmpreg = SPIx->CR1;
00005a 8802 LDRH r2,[r0,#0]
;;;129 /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
;;;130 tmpreg &= CR1_CLEAR_Mask;
00005c f402f402 AND r2,r2,#0x3040
;;;131 /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
;;;132 master/salve mode, CPOL and CPHA */
;;;133 /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
;;;134 /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
;;;135 /* Set LSBFirst bit according to SPI_FirstBit value */
;;;136 /* Set BR bits according to SPI_BaudRatePrescaler value */
;;;137 /* Set CPOL bit according to SPI_CPOL value */
;;;138 /* Set CPHA bit according to SPI_CPHA value */
;;;139 tmpreg |= (u16)((u32)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
000060 880b LDRH r3,[r1,#0]
000062 884c LDRH r4,[r1,#2]
000064 88cd LDRH r5,[r1,#6]
000066 4323 ORRS r3,r3,r4
000068 888c LDRH r4,[r1,#4]
00006a 432c ORRS r4,r4,r5
00006c 4323 ORRS r3,r3,r4
00006e 890c LDRH r4,[r1,#8]
000070 4323 ORRS r3,r3,r4
000072 894c LDRH r4,[r1,#0xa]
000074 4323 ORRS r3,r3,r4
000076 898c LDRH r4,[r1,#0xc]
000078 4323 ORRS r3,r3,r4
00007a 89cc LDRH r4,[r1,#0xe]
00007c 4323 ORRS r3,r3,r4
00007e 4313 ORRS r3,r3,r2
;;;140 SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
;;;141 SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
;;;142 SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
;;;143 /* Write to SPIx CR1 */
;;;144 SPIx->CR1 = tmpreg;
000080 8003 STRH r3,[r0,#0]
;;;145
;;;146 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
;;;147 SPIx->I2SCFGR &= SPI_Mode_Select;
000082 8b82 LDRH r2,[r0,#0x1c]
000084 f422f422 BIC r2,r2,#0x800
000088 8382 STRH r2,[r0,#0x1c]
;;;148
;;;149 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
;;;150 /* Write to SPIx CRCPOLY */
;;;151 SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
00008a 8a09 LDRH r1,[r1,#0x10]
00008c 8201 STRH r1,[r0,#0x10]
;;;152 }
00008e bd30 POP {r4,r5,pc}
;;;153
ENDP
I2S_Init PROC
;;;166 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
;;;167 {
000090 b5f0 PUSH {r4-r7,lr}
000092 b085 SUB sp,sp,#0x14
000094 4605 MOV r5,r0
000096 460c MOV r4,r1
;;;168 u16 tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
000098 2002 MOVS r0,#2
00009a 2100 MOVS r1,#0
00009c 2601 MOVS r6,#1
;;;169 u32 tmp = 0;
;;;170 RCC_ClocksTypeDef RCC_Clocks;
;;;171
;;;172 /* Check the I2S parameters */
;;;173 assert_param(IS_SPI_23_PERIPH(SPIx));
;;;174 assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
;;;175 assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
;;;176 assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
;;;177 assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
;;;178 assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
;;;179 assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
;;;180
;;;181 /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
;;;182
;;;183 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
;;;184 SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
00009e 8baa LDRH r2,[r5,#0x1c]
0000a0 f24ff24f MOV r3,#0xf040
0000a4 401a ANDS r2,r2,r3
0000a6 83aa STRH r2,[r5,#0x1c]
;;;185 SPIx->I2SPR = 0x0002;
0000a8 2202 MOVS r2,#2
0000aa 842a STRH r2,[r5,#0x20]
;;;186
;;;187 /* Get the I2SCFGR register value */
;;;188 tmpreg = SPIx->I2SCFGR;
0000ac 8baf LDRH r7,[r5,#0x1c]
;;;189
;;;190 /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
;;;191 if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
0000ae 8922 LDRH r2,[r4,#8]
0000b0 2a02 CMP r2,#2
0000b2 d024 BEQ |L1.254|
;;;192 {
;;;193 i2sodd = (u16)0;
;;;194 i2sdiv = (u16)2;
;;;195 }
;;;196 /* If the requested audio frequency is not the default, compute the prescaler */
;;;197 else
;;;198 {
;;;199 /* Check the frame length (For the Prescaler computing) */
;;;200 if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
0000b4 88a0 LDRH r0,[r4,#4]
0000b6 b100 CBZ r0,|L1.186|
;;;201 {
;;;202 /* Packet length is 16 bits */
;;;203 packetlength = 1;
;;;204 }
;;;205 else
;;;206 {
;;;207 /* Packet length is 32 bits */
;;;208 packetlength = 2;
0000b8 2602 MOVS r6,#2
|L1.186|
;;;209 }
;;;210 /* Get System Clock frequency */
;;;211 RCC_GetClocksFreq(&RCC_Clocks);
0000ba 4668 MOV r0,sp
0000bc f7fff7ff BL RCC_GetClocksFreq
;;;212
;;;213 /* Compute the Real divider depending on the MCLK output state with a flaoting point */
;;;214 if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
0000c0 88e0 LDRH r0,[r4,#6]
0000c2 210a MOVS r1,#0xa
0000c4 f5b0f5b0 CMP r0,#0x200
0000c8 d108 BNE |L1.220|
;;;215 {
;;;216 /* MCLK output is enabled */
;;;217 tmp = (u16)(((10 * RCC_Clocks.SYSCLK_Frequency) / (256 * I2S_InitStruct->I2S_AudioFreq)) + 5);
0000ca 9800 LDR r0,[sp,#0]
0000cc 8922 LDRH r2,[r4,#8]
0000ce 4348 MULS r0,r1,r0
0000d0 0212 LSLS r2,r2,#8
0000d2 fbb0fbb0 UDIV r0,r0,r2
0000d6 1d40 ADDS r0,r0,#5
0000d8 b280 UXTH r0,r0
0000da e008 B |L1.238|
|L1.220|
;;;218 }
;;;219 else
;;;220 {
;;;221 /* MCLK output is disabled */
;;;222 tmp = (u16)(((10 * RCC_Clocks.SYSCLK_Frequency) / (32 * packetlength * I2S_InitStruct->I2S_AudioFreq)) + 5);
0000dc 8920 LDRH r0,[r4,#8]
0000de 0172 LSLS r2,r6,#5
0000e0 4342 MULS r2,r0,r2
0000e2 9800 LDR r0,[sp,#0]
0000e4 4348 MULS r0,r1,r0
0000e6 fbb0fbb0 UDIV r0,r0,r2
0000ea 1d40 ADDS r0,r0,#5
0000ec b280 UXTH r0,r0
|L1.238|
;;;223 }
;;;224
;;;225 /* Remove the flaoting point */
;;;226 tmp = tmp/10;
0000ee fbb0fbb0 UDIV r0,r0,r1
;;;227
;;;228 /* Check the parity of the divider */
;;;229 i2sodd = (u16)(tmp & (u16)0x0001);
0000f2 f000f000 AND r1,r0,#1
;;;230
;;;231 /* Compute the i2sdiv prescaler */
;;;232 i2sdiv = (u16)((tmp - i2sodd) / 2);
0000f6 1a40 SUBS r0,r0,r1
0000f8 f3c0f3c0 UBFX r0,r0,#1,#16
;;;233
;;;234 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
;;;235 i2sodd = (u16) (i2sodd << 8);
0000fc 0209 LSLS r1,r1,#8
|L1.254|
;;;236 }
;;;237
;;;238 /* Test if the divider is 1 or 0 */
;;;239 if ((i2sdiv < 2) || (i2sdiv > 0xFF))
0000fe 1e82 SUBS r2,r0,#2
000100 2afe CMP r2,#0xfe
000102 d301 BCC |L1.264|
;;;240 {
;;;241 /* Set the default values */
;;;242 i2sdiv = 2;
000104 2002 MOVS r0,#2
;;;243 i2sodd = 0;
000106 2100 MOVS r1,#0
|L1.264|
;;;244 }
;;;245
;;;246 /* Write to SPIx I2SPR register the computed value */
;;;247 SPIx->I2SPR = (u16)(i2sdiv | i2sodd | I2S_InitStruct->I2S_MCLKOutput);
000108 88e2 LDRH r2,[r4,#6]
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