📄 cpu_c.txt
字号:
|L1.704|
;;;524 break;
;;;525
;;;526
;;;527 /* ---------------- EXTERNAL INTERRUPT ---------------- */
;;;528 default:
;;;529 pos_max = CPU_INT_SRC_POS_MAX;
0002c0 6868 LDR r0,[r5,#4]
0002c2 1c40 ADDS r0,r0,#1
0002c4 2101 MOVS r1,#1
0002c6 eb01eb01 ADD r0,r1,r0,LSL #5
0002ca b2c0 UXTB r0,r0
;;;530 if (pos < pos_max) { /* See Note #3. */
0002cc 4286 CMP r6,r0
0002ce d21a BCS |L1.774|
;;;531 group = (pos - 16) / 4;
0002d0 3e10 SUBS r6,r6,#0x10
0002d2 17f0 ASRS r0,r6,#31
0002d4 eb06eb06 ADD r0,r6,r0,LSR #30
0002d8 f3c0f3c0 UBFX r7,r0,#2,#8
;;;532 nbr = (pos - 16) % 4;
0002dc f020f020 BIC r0,r0,#3
0002e0 1a36 SUBS r6,r6,r0
;;;533
;;;534 CPU_CRITICAL_ENTER();
0002e2 f7fff7ff BL CPU_SR_Save
;;;535 temp = CPU_REG_NVIC_PRIO(group);
0002e6 eb05eb05 ADD r1,r5,r7,LSL #2
0002ea f8d1f8d1 LDR r3,[r1,#0x400]
;;;536 temp &= ~(DEF_OCTET_MASK << (nbr * DEF_OCTET_NBR_BITS));
0002ee 00f2 LSLS r2,r6,#3
0002f0 25ff MOVS r5,#0xff
0002f2 4095 LSLS r5,r5,r2
0002f4 43ab BICS r3,r3,r5
;;;537 temp |= (prio << (nbr * DEF_OCTET_NBR_BITS));
0002f6 4094 LSLS r4,r4,r2
0002f8 431c ORRS r4,r4,r3
;;;538 CPU_REG_NVIC_PRIO(group) = temp;
0002fa f8c1f8c1 STR r4,[r1,#0x400]
;;;539 CPU_CRITICAL_EXIT();
0002fe e8bde8bd POP {r4-r8,lr}
000302 f7fff7ff B.W CPU_SR_Restore
|L1.774|
;;;540 }
;;;541 break;
;;;542 }
;;;543 }
000306 e709 B |L1.284|
;;;544
ENDP
CPU_IntSrcPrioGet PROC
;;;567 CPU_INT16S CPU_IntSrcPrioGet (CPU_INT08U pos)
;;;568 {
000308 b570 PUSH {r4-r6,lr}
;;;569 #if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
;;;570 CPU_SR cpu_sr;
;;;571 #endif
;;;572 CPU_INT08U group;
;;;573 CPU_INT08U nbr;
;;;574 CPU_INT08U pos_max;
;;;575 CPU_INT16S prio;
;;;576 CPU_INT32U prio_32;
;;;577 CPU_INT32U temp;
;;;578
;;;579
;;;580 switch (pos) {
00030a 4c3a LDR r4,|L1.1012|
00030c f04ff04f MOV r5,#0xe000e000
000310 2810 CMP r0,#0x10
000312 d24b BCS |L1.940|
000314 e8dfe8df TBB [pc,r0]
000318 66080b0e DCB 0x66,0x08,0x0b,0x0e
00031c 11192266 DCB 0x11,0x19,0x22,0x66
000320 66666629 DCB 0x66,0x66,0x66,0x29
000324 31663942 DCB 0x31,0x66,0x39,0x42
;;;581 case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
;;;582 case CPU_INT_RSVD_07:
;;;583 case CPU_INT_RSVD_08:
;;;584 case CPU_INT_RSVD_09:
;;;585 case CPU_INT_RSVD_10:
;;;586 case CPU_INT_RSVD_13:
;;;587 prio = DEF_INT_16S_MIN_VAL;
;;;588 break;
;;;589
;;;590
;;;591 /* ----------------- SYSTEM EXCEPTIONS ---------------- */
;;;592 case CPU_INT_RESET: /* Reset (see Note #2). */
;;;593 prio = -3;
000328 f06ff06f MVN r4,#2
;;;594 break;
00032c e05a B |L1.996|
;;;595
;;;596 case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
;;;597 prio = -2;
00032e f06ff06f MVN r4,#1
;;;598 break;
000332 e057 B |L1.996|
;;;599
;;;600 case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
;;;601 prio = -1;
000334 f04ff04f MOV r4,#0xffffffff
;;;602 break;
000338 e054 B |L1.996|
;;;603
;;;604
;;;605 case CPU_INT_MEM: /* Memory management. */
;;;606 CPU_CRITICAL_ENTER();
00033a f7fff7ff BL CPU_SR_Save
;;;607 temp = CPU_REG_NVIC_SHPRI1;
00033e f8d5f8d5 LDR r1,[r5,#0xd18]
;;;608 prio = (temp >> (0 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
000342 b2cc UXTB r4,r1
;;;609 CPU_CRITICAL_EXIT();
000344 f7fff7ff BL CPU_SR_Restore
;;;610 break;
000348 e04c B |L1.996|
;;;611
;;;612
;;;613 case CPU_INT_BUSFAULT: /* Bus fault. */
;;;614 CPU_CRITICAL_ENTER();
00034a f7fff7ff BL CPU_SR_Save
;;;615 temp = CPU_REG_NVIC_SHPRI1;
00034e f8d5f8d5 LDR r1,[r5,#0xd18]
;;;616 prio = (temp >> (1 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
000352 f3c1f3c1 UBFX r4,r1,#8,#8
;;;617 CPU_CRITICAL_EXIT();
000356 f7fff7ff BL CPU_SR_Restore
;;;618 break;
00035a e043 B |L1.996|
;;;619
;;;620
;;;621 case CPU_INT_USAGEFAULT: /* Usage fault. */
;;;622 CPU_CRITICAL_ENTER();
00035c f7fff7ff BL CPU_SR_Save
;;;623 temp = CPU_REG_NVIC_SHPRI1;
000360 f8d5f8d5 LDR r0,[r5,#0xd18]
;;;624 prio = (temp >> (2 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
000364 f3c0f3c0 UBFX r4,r0,#16,#8
;;;625 break;
000368 e03c B |L1.996|
;;;626
;;;627 case CPU_INT_SVCALL: /* SVCall. */
;;;628 CPU_CRITICAL_ENTER();
00036a f7fff7ff BL CPU_SR_Save
;;;629 temp = CPU_REG_NVIC_SHPRI2;
00036e f8d5f8d5 LDR r1,[r5,#0xd1c]
;;;630 prio = (temp >> (3 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
000372 0e0c LSRS r4,r1,#24
;;;631 CPU_CRITICAL_EXIT();
000374 f7fff7ff BL CPU_SR_Restore
;;;632 break;
000378 e034 B |L1.996|
;;;633
;;;634 case CPU_INT_DBGMON: /* Debug monitor. */
;;;635 CPU_CRITICAL_ENTER();
00037a f7fff7ff BL CPU_SR_Save
;;;636 temp = CPU_REG_NVIC_SHPRI3;
00037e f8d5f8d5 LDR r1,[r5,#0xd20]
;;;637 prio = (temp >> (0 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
000382 b2cc UXTB r4,r1
;;;638 CPU_CRITICAL_EXIT();
000384 f7fff7ff BL CPU_SR_Restore
;;;639 break;
000388 e02c B |L1.996|
;;;640
;;;641 case CPU_INT_PENDSV: /* PendSV. */
;;;642 CPU_CRITICAL_ENTER();
00038a f7fff7ff BL CPU_SR_Save
;;;643 temp = CPU_REG_NVIC_SHPRI3;
00038e f8d5f8d5 LDR r1,[r5,#0xd20]
;;;644 prio = (temp >> (2 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
000392 f3c1f3c1 UBFX r4,r1,#16,#8
;;;645 CPU_CRITICAL_EXIT();
000396 f7fff7ff BL CPU_SR_Restore
;;;646 break;
00039a e023 B |L1.996|
;;;647
;;;648 case CPU_INT_SYSTICK: /* SysTick. */
;;;649 CPU_CRITICAL_ENTER();
00039c f7fff7ff BL CPU_SR_Save
;;;650 temp = CPU_REG_NVIC_SHPRI3;
0003a0 f8d5f8d5 LDR r1,[r5,#0xd20]
;;;651 prio = (temp >> (3 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
0003a4 0e0c LSRS r4,r1,#24
;;;652 CPU_CRITICAL_EXIT();
0003a6 f7fff7ff BL CPU_SR_Restore
;;;653 break;
0003aa e01b B |L1.996|
|L1.940|
;;;654
;;;655
;;;656 /* ---------------- EXTERNAL INTERRUPT ---------------- */
;;;657 default:
;;;658 pos_max = CPU_INT_SRC_POS_MAX;
0003ac 6869 LDR r1,[r5,#4]
0003ae 1c49 ADDS r1,r1,#1
0003b0 2201 MOVS r2,#1
0003b2 eb02eb02 ADD r1,r2,r1,LSL #5
0003b6 b2c9 UXTB r1,r1
;;;659 if (pos < pos_max) { /* See Note #3. */
0003b8 4288 CMP r0,r1
0003ba d213 BCS |L1.996|
;;;660 group = (pos - 16) / 4;
0003bc 3810 SUBS r0,r0,#0x10
0003be 17c1 ASRS r1,r0,#31
0003c0 eb00eb00 ADD r1,r0,r1,LSR #30
0003c4 f3c1f3c1 UBFX r4,r1,#2,#8
;;;661 nbr = (pos - 16) % 4;
0003c8 f021f021 BIC r1,r1,#3
0003cc 1a46 SUBS r6,r0,r1
;;;662
;;;663 CPU_CRITICAL_ENTER();
0003ce f7fff7ff BL CPU_SR_Save
;;;664 temp = CPU_REG_NVIC_PRIO(group);
0003d2 eb05eb05 ADD r1,r5,r4,LSL #2
0003d6 f8d1f8d1 LDR r4,[r1,#0x400]
;;;665 CPU_CRITICAL_EXIT();
0003da f7fff7ff BL CPU_SR_Restore
;;;666
;;;667 prio = (temp >> (nbr * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
0003de 00f0 LSLS r0,r6,#3
0003e0 40c4 LSRS r4,r4,r0
0003e2 b2e4 UXTB r4,r4
|L1.996|
;;;668 } else {
;;;669 prio = DEF_INT_16S_MIN_VAL;
;;;670 }
;;;671 break;
;;;672 }
;;;673
;;;674 if (prio >= 0) {
0003e4 2c00 CMP r4,#0
0003e6 db03 BLT |L1.1008|
;;;675 prio_32 = CPU_RevBits((CPU_INT32U)prio);
0003e8 4620 MOV r0,r4
0003ea f7fff7ff BL CPU_RevBits
;;;676 prio = (CPU_INT16S)(prio_32 >> (3 * DEF_OCTET_NBR_BITS));
0003ee 0e04 LSRS r4,r0,#24
|L1.1008|
;;;677 }
;;;678
;;;679 return (prio);
0003f0 4620 MOV r0,r4
;;;680 }
0003f2 bd70 POP {r4-r6,pc}
ENDP
|L1.1012|
0003f4 ffff8000 DCD 0xffff8000
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