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📄 cpu_c.txt

📁 stm32 ucos 精简移殖版本 不需作任何修改直接便可运行。包含串口 定时器
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;;;353    
;;;354    
;;;355                                                                    /* ----------------- SYSTEM EXCEPTIONS ---------------- */
;;;356            case CPU_INT_RESET:                                     /* Reset (see Note #2).                                 */
;;;357            case CPU_INT_NMI:                                       /* Non-maskable interrupt (see Note #2).                */
;;;358            case CPU_INT_HFAULT:                                    /* Hard fault (see Note #2).                            */
;;;359            case CPU_INT_SVCALL:                                    /* SVCall (see Note #2).                                */
;;;360            case CPU_INT_DBGMON:                                    /* Debug monitor (see Note #2).                         */
;;;361            case CPU_INT_PENDSV:                                    /* PendSV (see Note #2).                                */
;;;362                 break;
;;;363    
;;;364            case CPU_INT_MEM:                                       /* Memory management.                                   */
;;;365                 CPU_CRITICAL_ENTER();
000140  f7fff7ff          BL       CPU_SR_Save
;;;366                 CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_MEMFAULTENA;
000144  f8d4f8d4          LDR      r1,[r4,#0xd24]
000148  f441f441          ORR      r1,r1,#0x10000
00014c  f8c4f8c4          STR      r1,[r4,#0xd24]
;;;367                 CPU_CRITICAL_EXIT();
000150  e8bde8bd          POP      {r4-r8,lr}
000154  f7fff7ff          B.W      CPU_SR_Restore
;;;368                 break;
;;;369    
;;;370            case CPU_INT_BUSFAULT:                                  /* Bus fault.                                           */
;;;371                 CPU_CRITICAL_ENTER();
000158  f7fff7ff          BL       CPU_SR_Save
;;;372                 CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_BUSFAULTENA;
00015c  f8d4f8d4          LDR      r1,[r4,#0xd24]
000160  f441f441          ORR      r1,r1,#0x20000
000164  f8c4f8c4          STR      r1,[r4,#0xd24]
;;;373                 CPU_CRITICAL_EXIT();
000168  e8bde8bd          POP      {r4-r8,lr}
00016c  f7fff7ff          B.W      CPU_SR_Restore
;;;374                 break;
;;;375    
;;;376            case CPU_INT_USAGEFAULT:                                /* Usage fault.                                         */
;;;377                 CPU_CRITICAL_ENTER();
000170  f7fff7ff          BL       CPU_SR_Save
;;;378                 CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_USGFAULTENA;
000174  f8d4f8d4          LDR      r1,[r4,#0xd24]
000178  f441f441          ORR      r1,r1,#0x40000
00017c  f8c4f8c4          STR      r1,[r4,#0xd24]
;;;379                 CPU_CRITICAL_EXIT();
000180  e8bde8bd          POP      {r4-r8,lr}
000184  f7fff7ff          B.W      CPU_SR_Restore
;;;380                 break;
;;;381    
;;;382            case CPU_INT_SYSTICK:                                   /* SysTick.                                             */
;;;383                 CPU_CRITICAL_ENTER();
000188  f7fff7ff          BL       CPU_SR_Save
;;;384                 CPU_REG_NVIC_ST_CTRL |= CPU_REG_NVIC_ST_CTRL_ENABLE;
00018c  6921              LDR      r1,[r4,#0x10]
00018e  f041f041          ORR      r1,r1,#1
000192  6121              STR      r1,[r4,#0x10]
;;;385                 CPU_CRITICAL_EXIT();
000194  e8bde8bd          POP      {r4-r8,lr}
000198  f7fff7ff          B.W      CPU_SR_Restore
                  |L1.412|
;;;386                 break;
;;;387    
;;;388    
;;;389                                                                    /* ---------------- EXTERNAL INTERRUPT ---------------- */
;;;390            default:
;;;391                pos_max = CPU_INT_SRC_POS_MAX;
00019c  6861              LDR      r1,[r4,#4]
00019e  1c49              ADDS     r1,r1,#1
0001a0  2501              MOVS     r5,#1
0001a2  eb05eb05          ADD      r1,r5,r1,LSL #5
0001a6  b2c9              UXTB     r1,r1
;;;392                if (pos < pos_max) {                                /* See Note #3.                                         */
0001a8  4288              CMP      r0,r1
0001aa  d2b7              BCS      |L1.284|
;;;393                     group = (pos - 16) / 32;
0001ac  3810              SUBS     r0,r0,#0x10
0001ae  17c1              ASRS     r1,r0,#31
0001b0  eb00eb00          ADD      r1,r0,r1,LSR #27
0001b4  f3c1f3c1          UBFX     r6,r1,#5,#8
;;;394                     nbr   = (pos - 16) % 32;
0001b8  f021f021          BIC      r1,r1,#0x1f
0001bc  1a47              SUBS     r7,r0,r1
;;;395    
;;;396                     CPU_CRITICAL_ENTER();
0001be  f7fff7ff          BL       CPU_SR_Save
;;;397                     CPU_REG_NVIC_SETEN(group) = DEF_BIT(nbr);
0001c2  40bd              LSLS     r5,r5,r7
0001c4  eb04eb04          ADD      r1,r4,r6,LSL #2
0001c8  f8c1f8c1          STR      r5,[r1,#0x100]
;;;398                     CPU_CRITICAL_EXIT();
0001cc  e8bde8bd          POP      {r4-r8,lr}
0001d0  f7fff7ff          B.W      CPU_SR_Restore
;;;399                 }
;;;400                 break;
;;;401        }
;;;402    }
0001d4  e7a2              B        |L1.284|
;;;403    
                          ENDP

                  CPU_IntSrcPrioSet PROC
;;;432                             CPU_INT08U  prio)
;;;433    {
0001d6  e92de92d          PUSH     {r4-r8,lr}
0001da  4606              MOV      r6,r0
0001dc  4608              MOV      r0,r1
;;;434    #if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
;;;435        CPU_SR      cpu_sr;
;;;436    #endif
;;;437        CPU_INT08U  group;
;;;438        CPU_INT08U  nbr;
;;;439        CPU_INT08U  pos_max;
;;;440        CPU_INT32U  prio_32;
;;;441        CPU_INT32U  temp;
;;;442    
;;;443    
;;;444        prio_32 = CPU_RevBits((CPU_INT08U)prio);
0001de  f7fff7ff          BL       CPU_RevBits
;;;445        prio    = (CPU_INT08U)(prio_32 >> (3 * DEF_OCTET_NBR_BITS));
0001e2  0e04              LSRS     r4,r0,#24
;;;446    
;;;447        switch (pos) {
0001e4  f04ff04f          MOV      r5,#0xe000e000
0001e8  2e10              CMP      r6,#0x10
0001ea  d269              BCS      |L1.704|
0001ec  e8dfe8df          TBB      [pc,r6]
0001f0  8b8b8b8b          DCB      0x8b,0x8b,0x8b,0x8b
0001f4  0815238b          DCB      0x08,0x15,0x23,0x8b
0001f8  8b8b8b31          DCB      0x8b,0x8b,0x8b,0x31
0001fc  3f8b4c5a          DCB      0x3f,0x8b,0x4c,0x5a
;;;448            case CPU_INT_STK_PTR:                                   /* ---------------- INVALID OR RESERVED --------------- */
;;;449            case CPU_INT_RSVD_07:
;;;450            case CPU_INT_RSVD_08:
;;;451            case CPU_INT_RSVD_09:
;;;452            case CPU_INT_RSVD_10:
;;;453            case CPU_INT_RSVD_13:
;;;454                 break;
;;;455    
;;;456    
;;;457                                                                    /* ----------------- SYSTEM EXCEPTIONS ---------------- */
;;;458            case CPU_INT_RESET:                                     /* Reset (see Note #2).                                 */
;;;459            case CPU_INT_NMI:                                       /* Non-maskable interrupt (see Note #2).                */
;;;460            case CPU_INT_HFAULT:                                    /* Hard fault (see Note #2).                            */
;;;461                 break;
;;;462    
;;;463            case CPU_INT_MEM:                                       /* Memory management.                                   */
;;;464                 CPU_CRITICAL_ENTER();
000200  f7fff7ff          BL       CPU_SR_Save
;;;465                 temp                 = CPU_REG_NVIC_SHPRI1;
000204  f8d5f8d5          LDR      r1,[r5,#0xd18]
;;;466                 temp                &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
000208  f021f021          BIC      r1,r1,#0xff
;;;467                 temp                |=  (prio           << (0 * DEF_OCTET_NBR_BITS));
00020c  4321              ORRS     r1,r1,r4
;;;468                 CPU_REG_NVIC_SHPRI1  = temp;
00020e  f8c5f8c5          STR      r1,[r5,#0xd18]
;;;469                 CPU_CRITICAL_EXIT();
000212  e8bde8bd          POP      {r4-r8,lr}
000216  f7fff7ff          B.W      CPU_SR_Restore
;;;470                 break;
;;;471    
;;;472            case CPU_INT_BUSFAULT:                                  /* Bus fault.                                           */
;;;473                 CPU_CRITICAL_ENTER();
00021a  f7fff7ff          BL       CPU_SR_Save
;;;474                 temp                 = CPU_REG_NVIC_SHPRI1;
00021e  f8d5f8d5          LDR      r1,[r5,#0xd18]
;;;475                 temp                &= ~(DEF_OCTET_MASK << (1 * DEF_OCTET_NBR_BITS));
000222  f421f421          BIC      r1,r1,#0xff00
;;;476                 temp                |=  (prio           << (1 * DEF_OCTET_NBR_BITS));
000226  ea41ea41          ORR      r1,r1,r4,LSL #8
;;;477                 CPU_REG_NVIC_SHPRI1  = temp;
00022a  f8c5f8c5          STR      r1,[r5,#0xd18]
;;;478                 CPU_CRITICAL_EXIT();
00022e  e8bde8bd          POP      {r4-r8,lr}
000232  f7fff7ff          B.W      CPU_SR_Restore
;;;479                 break;
;;;480    
;;;481            case CPU_INT_USAGEFAULT:                                /* Usage fault.                                         */
;;;482                 CPU_CRITICAL_ENTER();
000236  f7fff7ff          BL       CPU_SR_Save
;;;483                 temp                 = CPU_REG_NVIC_SHPRI1;
00023a  f8d5f8d5          LDR      r1,[r5,#0xd18]
;;;484                 temp                &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
00023e  f421f421          BIC      r1,r1,#0xff0000
;;;485                 temp                |=  (prio           << (2 * DEF_OCTET_NBR_BITS));
000242  ea41ea41          ORR      r1,r1,r4,LSL #16
;;;486                 CPU_REG_NVIC_SHPRI1  = temp;
000246  f8c5f8c5          STR      r1,[r5,#0xd18]
;;;487                 CPU_CRITICAL_EXIT();
00024a  e8bde8bd          POP      {r4-r8,lr}
00024e  f7fff7ff          B.W      CPU_SR_Restore
;;;488                 break;
;;;489    
;;;490            case CPU_INT_SVCALL:                                    /* SVCall.                                              */
;;;491                 CPU_CRITICAL_ENTER();
000252  f7fff7ff          BL       CPU_SR_Save
;;;492                 temp                 = CPU_REG_NVIC_SHPRI2;
000256  f8d5f8d5          LDR      r1,[r5,#0xd1c]
;;;493                 temp                &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
00025a  f021f021          BIC      r1,r1,#0xff000000
;;;494                 temp                |=  (prio                       << (3 * DEF_OCTET_NBR_BITS));
00025e  ea41ea41          ORR      r1,r1,r4,LSL #24
;;;495                 CPU_REG_NVIC_SHPRI2  = temp;
000262  f8c5f8c5          STR      r1,[r5,#0xd1c]
;;;496                 CPU_CRITICAL_EXIT();
000266  e8bde8bd          POP      {r4-r8,lr}
00026a  f7fff7ff          B.W      CPU_SR_Restore
;;;497                 break;
;;;498    
;;;499            case CPU_INT_DBGMON:                                    /* Debug monitor.                                       */
;;;500                 CPU_CRITICAL_ENTER();
00026e  f7fff7ff          BL       CPU_SR_Save
;;;501                 temp                = CPU_REG_NVIC_SHPRI3;
000272  f8d5f8d5          LDR      r1,[r5,#0xd20]
;;;502                 temp                &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
000276  f021f021          BIC      r1,r1,#0xff
;;;503                 temp                |=  (prio           << (0 * DEF_OCTET_NBR_BITS));
00027a  4321              ORRS     r1,r1,r4
;;;504                 CPU_REG_NVIC_SHPRI3  = temp;
00027c  f8c5f8c5          STR      r1,[r5,#0xd20]
;;;505                 CPU_CRITICAL_EXIT();
000280  e8bde8bd          POP      {r4-r8,lr}
000284  f7fff7ff          B.W      CPU_SR_Restore
;;;506                 break;
;;;507    
;;;508            case CPU_INT_PENDSV:                                    /* PendSV.                                              */
;;;509                 CPU_CRITICAL_ENTER();
000288  f7fff7ff          BL       CPU_SR_Save
;;;510                 temp                 = CPU_REG_NVIC_SHPRI3;
00028c  f8d5f8d5          LDR      r1,[r5,#0xd20]
;;;511                 temp                &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
000290  f421f421          BIC      r1,r1,#0xff0000
;;;512                 temp                |=  (prio           << (2 * DEF_OCTET_NBR_BITS));
000294  ea41ea41          ORR      r1,r1,r4,LSL #16
;;;513                 CPU_REG_NVIC_SHPRI3  = temp;
000298  f8c5f8c5          STR      r1,[r5,#0xd20]
;;;514                 CPU_CRITICAL_EXIT();
00029c  e8bde8bd          POP      {r4-r8,lr}
0002a0  f7fff7ff          B.W      CPU_SR_Restore
;;;515                 break;
;;;516    
;;;517            case CPU_INT_SYSTICK:                                   /* SysTick.                                             */
;;;518                 CPU_CRITICAL_ENTER();
0002a4  f7fff7ff          BL       CPU_SR_Save
;;;519                 temp                 = CPU_REG_NVIC_SHPRI3;
0002a8  f8d5f8d5          LDR      r1,[r5,#0xd20]
;;;520                 temp                &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
0002ac  f021f021          BIC      r1,r1,#0xff000000
;;;521                 temp                |=  (prio                       << (3 * DEF_OCTET_NBR_BITS));
0002b0  ea41ea41          ORR      r1,r1,r4,LSL #24
;;;522                 CPU_REG_NVIC_SHPRI3  = temp;
0002b4  f8c5f8c5          STR      r1,[r5,#0xd20]
;;;523                 CPU_CRITICAL_EXIT();
0002b8  e8bde8bd          POP      {r4-r8,lr}
0002bc  f7fff7ff          B.W      CPU_SR_Restore

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