📄 cpu_c.txt
字号:
; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 919] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\output\cpu_c.o --depend=.\output\cpu_c.d --device=DARMSTM --apcs=interwork -O1 -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -IC:\Keil\ARM\INC\ST\STM32F10x --omf_browse=.\output\cpu_c.crf ..\..\..\..\..\uC-CPU\ARM-Cortex-M3\RealView\cpu_c.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
CPU_BitBandClr PROC
;;;131 CPU_INT08U bit_nbr)
;;;132 {
000000 b510 PUSH {r4,lr}
;;;133 CPU_ADDR bit_word_off;
;;;134 CPU_ADDR bit_word_addr;
;;;135
;;;136
;;;137 if ((addr >= CPU_BIT_BAND_SRAM_REG_LO) &&
000002 f1a0f1a0 SUB r2,r0,#0x20000000
000006 f44ff44f MOV r4,#0x100000
00000a 2300 MOVS r3,#0
00000c 42a2 CMP r2,r4
00000e d206 BCS |L1.30|
;;;138 (addr <= CPU_BIT_BAND_SRAM_REG_HI)) {
;;;139 bit_word_off = ((addr - CPU_BIT_BAND_SRAM_REG_LO) * 32) + (bit_nbr * 4);
000010 0150 LSLS r0,r2,#5
000012 eb00eb00 ADD r0,r0,r1,LSL #2
;;;140 bit_word_addr = CPU_BIT_BAND_SRAM_BASE + bit_word_off;
000016 f100f100 ADD r0,r0,#0x22000000
;;;141
;;;142 *(volatile CPU_INT32U *)(bit_word_addr) = 0;
00001a 6003 STR r3,[r0,#0]
|L1.28|
;;;143
;;;144 } else if ((addr >= CPU_BIT_BAND_PERIPH_REG_LO) &&
;;;145 (addr <= CPU_BIT_BAND_PERIPH_REG_HI)) {
;;;146 bit_word_off = ((addr - CPU_BIT_BAND_PERIPH_REG_LO) * 32) + (bit_nbr * 4);
;;;147 bit_word_addr = CPU_BIT_BAND_PERIPH_BASE + bit_word_off;
;;;148
;;;149 *(volatile CPU_INT32U *)(bit_word_addr) = 0;
;;;150 }
;;;151 }
00001c bd10 POP {r4,pc}
|L1.30|
00001e f1a0f1a0 SUB r0,r0,#0x40000000 ;144
000022 42a0 CMP r0,r4 ;144
000024 d2fa BCS |L1.28|
000026 0140 LSLS r0,r0,#5 ;146
000028 eb00eb00 ADD r0,r0,r1,LSL #2 ;146
00002c f100f100 ADD r0,r0,#0x42000000 ;147
000030 6003 STR r3,[r0,#0] ;149
000032 bd10 POP {r4,pc}
;;;152
ENDP
CPU_BitBandSet PROC
;;;173 CPU_INT08U bit_nbr)
;;;174 {
000034 b510 PUSH {r4,lr}
;;;175 CPU_ADDR bit_word_off;
;;;176 CPU_ADDR bit_word_addr;
;;;177
;;;178
;;;179 if ((addr >= CPU_BIT_BAND_SRAM_REG_LO) &&
000036 f1a0f1a0 SUB r2,r0,#0x20000000
00003a f44ff44f MOV r4,#0x100000
00003e 2301 MOVS r3,#1
000040 42a2 CMP r2,r4
000042 d206 BCS |L1.82|
;;;180 (addr <= CPU_BIT_BAND_SRAM_REG_HI)) {
;;;181 bit_word_off = ((addr - CPU_BIT_BAND_SRAM_REG_LO) * 32) + (bit_nbr * 4);
000044 0150 LSLS r0,r2,#5
000046 eb00eb00 ADD r0,r0,r1,LSL #2
;;;182 bit_word_addr = CPU_BIT_BAND_SRAM_BASE + bit_word_off;
00004a f100f100 ADD r0,r0,#0x22000000
;;;183
;;;184 *(volatile CPU_INT32U *)(bit_word_addr) = 1;
00004e 6003 STR r3,[r0,#0]
|L1.80|
;;;185
;;;186 } else if ((addr >= CPU_BIT_BAND_PERIPH_REG_LO) &&
;;;187 (addr <= CPU_BIT_BAND_PERIPH_REG_HI)) {
;;;188 bit_word_off = ((addr - CPU_BIT_BAND_PERIPH_REG_LO) * 32) + (bit_nbr * 4);
;;;189 bit_word_addr = CPU_BIT_BAND_PERIPH_BASE + bit_word_off;
;;;190
;;;191 *(volatile CPU_INT32U *)(bit_word_addr) = 1;
;;;192 }
;;;193 }
000050 bd10 POP {r4,pc}
|L1.82|
000052 f1a0f1a0 SUB r0,r0,#0x40000000 ;186
000056 42a0 CMP r0,r4 ;186
000058 d2fa BCS |L1.80|
00005a 0140 LSLS r0,r0,#5 ;188
00005c eb00eb00 ADD r0,r0,r1,LSL #2 ;188
000060 f100f100 ADD r0,r0,#0x42000000 ;189
000064 6003 STR r3,[r0,#0] ;191
000066 bd10 POP {r4,pc}
;;;194
ENDP
CPU_IntSrcDis PROC
;;;245 void CPU_IntSrcDis (CPU_INT08U pos)
;;;246 {
000068 e92de92d PUSH {r4-r8,lr}
;;;247 #if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
;;;248 CPU_SR cpu_sr;
;;;249 #endif
;;;250 CPU_INT08U group;
;;;251 CPU_INT08U pos_max;
;;;252 CPU_INT08U nbr;
;;;253
;;;254
;;;255 switch (pos) {
00006c f04ff04f MOV r4,#0xe000e000
000070 2810 CMP r0,#0x10
000072 d237 BCS |L1.228|
000074 e8dfe8df TBB [pc,r0]
000078 52525252 DCB 0x52,0x52,0x52,0x52
00007c 08142052 DCB 0x08,0x14,0x20,0x52
000080 52525252 DCB 0x52,0x52,0x52,0x52
000084 5252522c DCB 0x52,0x52,0x52,0x2c
;;;256 case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
;;;257 case CPU_INT_RSVD_07:
;;;258 case CPU_INT_RSVD_08:
;;;259 case CPU_INT_RSVD_09:
;;;260 case CPU_INT_RSVD_10:
;;;261 case CPU_INT_RSVD_13:
;;;262 break;
;;;263
;;;264
;;;265 /* ----------------- SYSTEM EXCEPTIONS ---------------- */
;;;266 case CPU_INT_RESET: /* Reset (see Note #2). */
;;;267 case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
;;;268 case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
;;;269 case CPU_INT_SVCALL: /* SVCall (see Note #2). */
;;;270 case CPU_INT_DBGMON: /* Debug monitor (see Note #2). */
;;;271 case CPU_INT_PENDSV: /* PendSV (see Note #2). */
;;;272 break;
;;;273
;;;274 case CPU_INT_MEM: /* Memory management. */
;;;275 CPU_CRITICAL_ENTER();
000088 f7fff7ff BL CPU_SR_Save
;;;276 CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_MEMFAULTENA;
00008c f8d4f8d4 LDR r1,[r4,#0xd24]
000090 f421f421 BIC r1,r1,#0x10000
000094 f8c4f8c4 STR r1,[r4,#0xd24]
;;;277 CPU_CRITICAL_EXIT();
000098 e8bde8bd POP {r4-r8,lr}
00009c f7fff7ff B.W CPU_SR_Restore
;;;278 break;
;;;279
;;;280 case CPU_INT_BUSFAULT: /* Bus fault. */
;;;281 CPU_CRITICAL_ENTER();
0000a0 f7fff7ff BL CPU_SR_Save
;;;282 CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_BUSFAULTENA;
0000a4 f8d4f8d4 LDR r1,[r4,#0xd24]
0000a8 f421f421 BIC r1,r1,#0x20000
0000ac f8c4f8c4 STR r1,[r4,#0xd24]
;;;283 CPU_CRITICAL_EXIT();
0000b0 e8bde8bd POP {r4-r8,lr}
0000b4 f7fff7ff B.W CPU_SR_Restore
;;;284 break;
;;;285
;;;286 case CPU_INT_USAGEFAULT: /* Usage fault. */
;;;287 CPU_CRITICAL_ENTER();
0000b8 f7fff7ff BL CPU_SR_Save
;;;288 CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_USGFAULTENA;
0000bc f8d4f8d4 LDR r1,[r4,#0xd24]
0000c0 f421f421 BIC r1,r1,#0x40000
0000c4 f8c4f8c4 STR r1,[r4,#0xd24]
;;;289 CPU_CRITICAL_EXIT();
0000c8 e8bde8bd POP {r4-r8,lr}
0000cc f7fff7ff B.W CPU_SR_Restore
;;;290 break;
;;;291
;;;292 case CPU_INT_SYSTICK: /* SysTick. */
;;;293 CPU_CRITICAL_ENTER();
0000d0 f7fff7ff BL CPU_SR_Save
;;;294 CPU_REG_NVIC_ST_CTRL &= ~CPU_REG_NVIC_ST_CTRL_ENABLE;
0000d4 6921 LDR r1,[r4,#0x10]
0000d6 f021f021 BIC r1,r1,#1
0000da 6121 STR r1,[r4,#0x10]
;;;295 CPU_CRITICAL_EXIT();
0000dc e8bde8bd POP {r4-r8,lr}
0000e0 f7fff7ff B.W CPU_SR_Restore
|L1.228|
;;;296 break;
;;;297
;;;298
;;;299 /* ---------------- EXTERNAL INTERRUPT ---------------- */
;;;300 default:
;;;301 pos_max = CPU_INT_SRC_POS_MAX;
0000e4 6861 LDR r1,[r4,#4]
0000e6 1c49 ADDS r1,r1,#1
0000e8 2501 MOVS r5,#1
0000ea eb05eb05 ADD r1,r5,r1,LSL #5
0000ee b2c9 UXTB r1,r1
;;;302 if (pos < pos_max) { /* See Note #3. */
0000f0 4288 CMP r0,r1
0000f2 d213 BCS |L1.284|
;;;303 group = (pos - 16) / 32;
0000f4 3810 SUBS r0,r0,#0x10
0000f6 17c1 ASRS r1,r0,#31
0000f8 eb00eb00 ADD r1,r0,r1,LSR #27
0000fc f3c1f3c1 UBFX r6,r1,#5,#8
;;;304 nbr = (pos - 16) % 32;
000100 f021f021 BIC r1,r1,#0x1f
000104 1a47 SUBS r7,r0,r1
;;;305
;;;306 CPU_CRITICAL_ENTER();
000106 f7fff7ff BL CPU_SR_Save
;;;307 CPU_REG_NVIC_CLREN(group) = DEF_BIT(nbr);
00010a 40bd LSLS r5,r5,r7
00010c eb04eb04 ADD r1,r4,r6,LSL #2
000110 f8c1f8c1 STR r5,[r1,#0x180]
;;;308 CPU_CRITICAL_EXIT();
000114 e8bde8bd POP {r4-r8,lr}
000118 f7fff7ff B.W CPU_SR_Restore
|L1.284|
;;;309 }
;;;310 break;
;;;311 }
;;;312 }
00011c e8bde8bd POP {r4-r8,pc}
;;;313
ENDP
CPU_IntSrcEn PROC
;;;335 void CPU_IntSrcEn (CPU_INT08U pos)
;;;336 {
000120 e92de92d PUSH {r4-r8,lr}
;;;337 #if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
;;;338 CPU_SR cpu_sr;
;;;339 #endif
;;;340 CPU_INT08U group;
;;;341 CPU_INT08U nbr;
;;;342 CPU_INT08U pos_max;
;;;343
;;;344
;;;345 switch (pos) {
000124 f04ff04f MOV r4,#0xe000e000
000128 2810 CMP r0,#0x10
00012a d237 BCS |L1.412|
00012c e8dfe8df TBB [pc,r0]
000130 52525252 DCB 0x52,0x52,0x52,0x52
000134 08142052 DCB 0x08,0x14,0x20,0x52
000138 52525252 DCB 0x52,0x52,0x52,0x52
00013c 5252522c DCB 0x52,0x52,0x52,0x2c
;;;346 case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
;;;347 case CPU_INT_RSVD_07:
;;;348 case CPU_INT_RSVD_08:
;;;349 case CPU_INT_RSVD_09:
;;;350 case CPU_INT_RSVD_10:
;;;351 case CPU_INT_RSVD_13:
;;;352 break;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -