📄 stm32f10x_nvic.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 919] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\output\stm32f10x_nvic.o --depend=.\output\stm32f10x_nvic.d --device=DARMSTM --apcs=interwork -O1 -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -IC:\Keil\ARM\INC\ST\STM32F10x --omf_browse=.\output\stm32f10x_nvic.crf ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_nvic.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
NVIC_DeInit PROC
;;;39 {
;;;40 u32 index = 0;
000000 2000 MOVS r0,#0
;;;41
;;;42 NVIC->ICER[0] = 0xFFFFFFFF;
000002 1e43 SUBS r3,r0,#1
000004 f04ff04f MOV r1,#0xe000e000
000008 f8c1f8c1 STR r3,[r1,#0x180]
;;;43 NVIC->ICER[1] = 0x0FFFFFFF;
00000c 091a LSRS r2,r3,#4
00000e f8c1f8c1 STR r2,[r1,#0x184]
;;;44 NVIC->ICPR[0] = 0xFFFFFFFF;
000012 f8c1f8c1 STR r3,[r1,#0x280]
;;;45 NVIC->ICPR[1] = 0x0FFFFFFF;
000016 f8c1f8c1 STR r2,[r1,#0x284]
;;;46
;;;47 for(index = 0; index < 0x0F; index++)
00001a 2200 MOVS r2,#0
|L1.28|
;;;48 {
;;;49 NVIC->IPR[index] = 0x00000000;
00001c eb01eb01 ADD r3,r1,r0,LSL #2
000020 f8c3f8c3 STR r2,[r3,#0x400]
000024 1c40 ADDS r0,r0,#1 ;47
000026 280f CMP r0,#0xf ;47
000028 d3f8 BCC |L1.28|
;;;50 }
;;;51 }
00002a 4770 BX lr
;;;52
ENDP
NVIC_SCBDeInit PROC
;;;62 {
;;;63 u32 index = 0x00;
00002c 2000 MOVS r0,#0
;;;64
;;;65 SCB->ICSR = 0x0A000000;
00002e 49a8 LDR r1,|L1.720|
000030 f04ff04f MOV r2,#0xa000000
000034 600a STR r2,[r1,#0]
;;;66 SCB->VTOR = 0x00000000;
000036 2200 MOVS r2,#0
000038 604a STR r2,[r1,#4]
;;;67 SCB->AIRCR = AIRCR_VECTKEY_MASK;
00003a 4ba6 LDR r3,|L1.724|
00003c 608b STR r3,[r1,#8]
;;;68 SCB->SCR = 0x00000000;
00003e 60ca STR r2,[r1,#0xc]
;;;69 SCB->CCR = 0x00000000;
000040 610a STR r2,[r1,#0x10]
000042 f6a1f6a1 SUB r1,r1,#0xd04
|L1.70|
;;;70 for(index = 0; index < 0x03; index++)
;;;71 {
;;;72 SCB->SHPR[index] = 0;
000046 eb01eb01 ADD r3,r1,r0,LSL #2
00004a f8c3f8c3 STR r2,[r3,#0xd18]
00004e 1c40 ADDS r0,r0,#1 ;70
000050 2803 CMP r0,#3 ;70
000052 d3f8 BCC |L1.70|
;;;73 }
;;;74 SCB->SHCSR = 0x00000000;
000054 f601f601 ADD r1,r1,#0xd24
000058 600a STR r2,[r1,#0]
;;;75 SCB->CFSR = 0xFFFFFFFF;
00005a f04ff04f MOV r0,#0xffffffff
00005e 6048 STR r0,[r1,#4]
;;;76 SCB->HFSR = 0xFFFFFFFF;
000060 6088 STR r0,[r1,#8]
;;;77 SCB->DFSR = 0xFFFFFFFF;
000062 60c8 STR r0,[r1,#0xc]
;;;78 }
000064 4770 BX lr
;;;79
ENDP
NVIC_PriorityGroupConfig PROC
;;;104 /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
;;;105 SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
000066 499b LDR r1,|L1.724|
000068 4308 ORRS r0,r0,r1
00006a 4999 LDR r1,|L1.720|
00006c 3108 ADDS r1,r1,#8
00006e 6008 STR r0,[r1,#0]
;;;106 }
000070 4770 BX lr
;;;107
ENDP
NVIC_Init PROC
;;;118 void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
;;;119 {
000072 b5f0 PUSH {r4-r7,lr}
;;;120 u32 tmppriority = 0x00, tmpreg = 0x00, tmpmask = 0x00;
;;;121 u32 tmppre = 0, tmpsub = 0x0F;
000074 230f MOVS r3,#0xf
;;;122
;;;123 /* Check the parameters */
;;;124 assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
;;;125 assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_InitStruct->NVIC_IRQChannel));
;;;126 assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
;;;127 assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
;;;128
;;;129 if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
000076 78c2 LDRB r2,[r0,#3]
000078 7801 LDRB r1,[r0,#0]
00007a f04ff04f MOV r4,#0xe000e000
00007e 2701 MOVS r7,#1
000080 b342 CBZ r2,|L1.212|
;;;130 {
;;;131 /* Compute the Corresponding IRQ Priority --------------------------------*/
;;;132 tmppriority = (0x700 - (SCB->AIRCR & (u32)0x700))>> 0x08;
000082 f8d4f8d4 LDR r2,[r4,#0xd0c]
000086 f402f402 AND r2,r2,#0x700
00008a f5c2f5c2 RSB r2,r2,#0x700
00008e 0a12 LSRS r2,r2,#8
;;;133 tmppre = (0x4 - tmppriority);
000090 f1c2f1c2 RSB r5,r2,#4
;;;134 tmpsub = tmpsub >> tmppriority;
000094 40d3 LSRS r3,r3,r2
;;;135
;;;136 tmppriority = (u32)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
000096 7842 LDRB r2,[r0,#1]
000098 40aa LSLS r2,r2,r5
;;;137 tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
00009a 7885 LDRB r5,[r0,#2]
00009c 401d ANDS r5,r5,r3
00009e 4315 ORRS r5,r5,r2
;;;138
;;;139 tmppriority = tmppriority << 0x04;
0000a0 012d LSLS r5,r5,#4
;;;140 tmppriority = ((u32)tmppriority) << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);
0000a2 078a LSLS r2,r1,#30
0000a4 0ed2 LSRS r2,r2,#27
0000a6 4095 LSLS r5,r5,r2
;;;141
;;;142 tmpreg = NVIC->IPR[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)];
0000a8 f021f021 BIC r1,r1,#3
0000ac 190b ADDS r3,r1,r4
0000ae f8d3f8d3 LDR r6,[r3,#0x400]
;;;143 tmpmask = (u32)0xFF << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);
0000b2 21ff MOVS r1,#0xff
0000b4 4091 LSLS r1,r1,r2
;;;144 tmpreg &= ~tmpmask;
0000b6 438e BICS r6,r6,r1
;;;145 tmppriority &= tmpmask;
0000b8 400d ANDS r5,r5,r1
;;;146 tmpreg |= tmppriority;
0000ba 432e ORRS r6,r6,r5
;;;147
;;;148 NVIC->IPR[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)] = tmpreg;
0000bc f8c3f8c3 STR r6,[r3,#0x400]
;;;149
;;;150 /* Enable the Selected IRQ Channels --------------------------------------*/
;;;151 NVIC->ISER[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =
0000c0 7800 LDRB r0,[r0,#0]
0000c2 f000f000 AND r1,r0,#0x1f
0000c6 408f LSLS r7,r7,r1
0000c8 0940 LSRS r0,r0,#5
0000ca eb04eb04 ADD r0,r4,r0,LSL #2
0000ce f8c0f8c0 STR r7,[r0,#0x100]
;;;152 (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);
;;;153 }
;;;154 else
;;;155 {
;;;156 /* Disable the Selected IRQ Channels -------------------------------------*/
;;;157 NVIC->ICER[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =
;;;158 (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);
;;;159 }
;;;160 }
0000d2 bdf0 POP {r4-r7,pc}
|L1.212|
0000d4 f001f001 AND r0,r1,#0x1f ;157
0000d8 4087 LSLS r7,r7,r0 ;157
0000da 0948 LSRS r0,r1,#5 ;157
0000dc eb04eb04 ADD r0,r4,r0,LSL #2 ;157
0000e0 f8c0f8c0 STR r7,[r0,#0x180] ;157
0000e4 bdf0 POP {r4-r7,pc}
;;;161
ENDP
NVIC_StructInit PROC
;;;172 /* NVIC_InitStruct members default value */
;;;173 NVIC_InitStruct->NVIC_IRQChannel = 0x00;
0000e6 2100 MOVS r1,#0
0000e8 7001 STRB r1,[r0,#0]
;;;174 NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority = 0x00;
0000ea 7041 STRB r1,[r0,#1]
;;;175 NVIC_InitStruct->NVIC_IRQChannelSubPriority = 0x00;
0000ec 7081 STRB r1,[r0,#2]
;;;176 NVIC_InitStruct->NVIC_IRQChannelCmd = DISABLE;
0000ee 70c1 STRB r1,[r0,#3]
;;;177 }
0000f0 4770 BX lr
;;;178
ENDP
NVIC_GetCurrentPendingIRQChannel PROC
;;;264 {
;;;265 return ((u16)((SCB->ICSR & (u32)0x003FF000) >> 0x0C));
0000f2 4877 LDR r0,|L1.720|
0000f4 6800 LDR r0,[r0,#0]
0000f6 f3c0f3c0 UBFX r0,r0,#12,#10
;;;266 }
0000fa 4770 BX lr
;;;267
ENDP
NVIC_GetIRQChannelPendingBitStatus PROC
;;;276 ITStatus NVIC_GetIRQChannelPendingBitStatus(u8 NVIC_IRQChannel)
;;;277 {
0000fc 4601 MOV r1,r0
;;;278 ITStatus pendingirqstatus = RESET;
0000fe 2000 MOVS r0,#0
;;;279 u32 tmp = 0x00;
;;;280
;;;281 /* Check the parameters */
;;;282 assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
;;;283
;;;284 tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));
000100 f001f001 AND r3,r1,#0x1f
000104 2201 MOVS r2,#1
000106 409a LSLS r2,r2,r3
;;;285
;;;286 if (((NVIC->ISPR[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp)
000108 0949 LSRS r1,r1,#5
00010a f04ff04f MOV r3,#0xe000e000
00010e eb03eb03 ADD r1,r3,r1,LSL #2
000112 f8d1f8d1 LDR r1,[r1,#0x200]
000116 438a BICS r2,r2,r1
000118 d100 BNE |L1.284|
;;;287 {
;;;288 pendingirqstatus = SET;
00011a 2001 MOVS r0,#1
|L1.284|
;;;289 }
;;;290 else
;;;291 {
;;;292 pendingirqstatus = RESET;
;;;293 }
;;;294 return pendingirqstatus;
;;;295 }
00011c 4770 BX lr
;;;296
ENDP
NVIC_SetIRQChannelPendingBit PROC
;;;308
;;;309 *(vu32*) 0xE000EF00 = (u32)NVIC_IRQChannel;
00011e 496e LDR r1,|L1.728|
000120 6008 STR r0,[r1,#0]
;;;310 }
000122 4770 BX lr
;;;311
ENDP
NVIC_ClearIRQChannelPendingBit PROC
;;;323
;;;324 NVIC->ICPR[(NVIC_IRQChannel >> 0x05)] = (u32)0x01 << (NVIC_IRQChannel & (u32)0x1F);
000124 f000f000 AND r2,r0,#0x1f
000128 2101 MOVS r1,#1
00012a 4091 LSLS r1,r1,r2
00012c 0940 LSRS r0,r0,#5
00012e f04ff04f MOV r2,#0xe000e000
000132 eb02eb02 ADD r0,r2,r0,LSL #2
000136 f8c0f8c0 STR r1,[r0,#0x280]
;;;325 }
00013a 4770 BX lr
;;;326
ENDP
NVIC_GetCurrentActiveHandler PROC
;;;336 {
;;;337 return ((u16)(SCB->ICSR & (u32)0x3FF));
00013c 4864 LDR r0,|L1.720|
00013e 6800 LDR r0,[r0,#0]
000140 f3c0f3c0 UBFX r0,r0,#0,#10
;;;338 }
000144 4770 BX lr
;;;339
ENDP
NVIC_GetIRQChannelActiveBitStatus PROC
;;;348 ITStatus NVIC_GetIRQChannelActiveBitStatus(u8 NVIC_IRQChannel)
;;;349 {
000146 4601 MOV r1,r0
;;;350 ITStatus activeirqstatus = RESET;
000148 2000 MOVS r0,#0
;;;351 u32 tmp = 0x00;
;;;352
;;;353 /* Check the parameters */
;;;354 assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
;;;355
;;;356 tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));
00014a f001f001 AND r3,r1,#0x1f
00014e 2201 MOVS r2,#1
000150 409a LSLS r2,r2,r3
;;;357
;;;358 if (((NVIC->IABR[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp )
000152 0949 LSRS r1,r1,#5
000154 f04ff04f MOV r3,#0xe000e000
000158 eb03eb03 ADD r1,r3,r1,LSL #2
00015c f8d1f8d1 LDR r1,[r1,#0x300]
000160 438a BICS r2,r2,r1
000162 d100 BNE |L1.358|
;;;359 {
;;;360 activeirqstatus = SET;
000164 2001 MOVS r0,#1
|L1.358|
;;;361 }
;;;362 else
;;;363 {
;;;364 activeirqstatus = RESET;
;;;365 }
;;;366 return activeirqstatus;
;;;367 }
000166 4770 BX lr
;;;368
ENDP
NVIC_GetCPUID PROC
;;;378 {
;;;379 return (SCB->CPUID);
000168 4859 LDR r0,|L1.720|
00016a 1f00 SUBS r0,r0,#4
00016c 6800 LDR r0,[r0,#0]
;;;380 }
00016e 4770 BX lr
;;;381
ENDP
NVIC_SetVectorTable PROC
;;;400
;;;401 SCB->VTOR = NVIC_VectTab | (Offset & (u32)0x1FFFFF80);
000170 4a5a LDR r2,|L1.732|
000172 4011 ANDS r1,r1,r2
000174 4301 ORRS r1,r1,r0
000176 4856 LDR r0,|L1.720|
000178 1d00 ADDS r0,r0,#4
00017a 6001 STR r1,[r0,#0]
;;;402 }
00017c 4770 BX lr
;;;403
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