📄 stm32f10x_adc.txt
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;;;1026 /* Calculate the mask to clear */
;;;1027 tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
00028a eb01eb01 ADD r4,r1,r1,LSL #1
00028e 40a6 LSLS r6,r6,r4
;;;1028 /* Clear the old discontinuous mode channel count */
;;;1029 tmpreg1 &= ~tmpreg2;
000290 43b5 BICS r5,r5,r6
;;;1030 /* Calculate the mask to set */
;;;1031 tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);
000292 40a3 LSLS r3,r3,r4
;;;1032 /* Set the discontinuous mode channel count */
;;;1033 tmpreg1 |= tmpreg2;
000294 431d ORRS r5,r5,r3
;;;1034 /* Store the new register value */
;;;1035 ADCx->SMPR2 = tmpreg1;
000296 6105 STR r5,[r0,#0x10]
|L1.664|
;;;1036 }
;;;1037
;;;1038 /* Rank configuration */
;;;1039 /* Get the old register value */
;;;1040 tmpreg1 = ADCx->JSQR;
000298 6b83 LDR r3,[r0,#0x38]
;;;1041 /* Get JL value: Number = JL+1 */
;;;1042 tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20;
00029a f3c3f3c3 UBFX r4,r3,#20,#2
;;;1043 /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
;;;1044 tmpreg2 = JSQR_JSQ_Set << (5 * (u8)((Rank + 3) - (tmpreg3 + 1)));
00029e 1b12 SUBS r2,r2,r4
0002a0 1c92 ADDS r2,r2,#2
0002a2 eb02eb02 ADD r2,r2,r2,LSL #2
0002a6 241f MOVS r4,#0x1f
0002a8 4094 LSLS r4,r4,r2
;;;1045 /* Clear the old JSQx bits for the selected rank */
;;;1046 tmpreg1 &= ~tmpreg2;
0002aa 43a3 BICS r3,r3,r4
;;;1047 /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
;;;1048 tmpreg2 = (u32)ADC_Channel << (5 * (u8)((Rank + 3) - (tmpreg3 + 1)));
0002ac 4091 LSLS r1,r1,r2
;;;1049 /* Set the JSQx bits for the selected rank */
;;;1050 tmpreg1 |= tmpreg2;
0002ae 430b ORRS r3,r3,r1
;;;1051 /* Store the new register value */
;;;1052 ADCx->JSQR = tmpreg1;
0002b0 6383 STR r3,[r0,#0x38]
;;;1053 }
0002b2 bd70 POP {r4-r6,pc}
;;;1054
ENDP
ADC_InjectedSequencerLengthConfig PROC
;;;1073 /* Get the old register value */
;;;1074 tmpreg1 = ADCx->JSQR;
0002b4 6b82 LDR r2,[r0,#0x38]
;;;1075 /* Clear the old injected sequnence lenght JL bits */
;;;1076 tmpreg1 &= JSQR_JL_Reset;
0002b6 f422f422 BIC r2,r2,#0x300000
;;;1077 /* Set the injected sequnence lenght JL bits */
;;;1078 tmpreg2 = Length - 1;
0002ba 1e49 SUBS r1,r1,#1
;;;1079 tmpreg1 |= tmpreg2 << 20;
0002bc ea42ea42 ORR r1,r2,r1,LSL #20
;;;1080 /* Store the new register value */
;;;1081 ADCx->JSQR = tmpreg1;
0002c0 6381 STR r1,[r0,#0x38]
;;;1082 }
0002c2 4770 BX lr
;;;1083
ENDP
ADC_SetInjectedOffset PROC
;;;1107 /* Set the selected injected channel data offset */
;;;1108 *((vu32 *)((*(u32*)&ADCx) + ADC_InjectedChannel)) = (u32)Offset;
0002c4 5042 STR r2,[r0,r1]
;;;1109 }
0002c6 4770 BX lr
;;;1110
ENDP
ADC_GetInjectedConversionValue PROC
;;;1130 /* Returns the selected injected channel conversion data value */
;;;1131 return (u16) (*(vu32*) (((*(u32*)&ADCx) + ADC_InjectedChannel + JDR_Offset)));
0002c8 4408 ADD r0,r0,r1
0002ca 6a80 LDR r0,[r0,#0x28]
0002cc b280 UXTH r0,r0
;;;1132 }
0002ce 4770 BX lr
;;;1133
ENDP
ADC_AnalogWatchdogCmd PROC
;;;1166 /* Get the old register value */
;;;1167 tmpreg = ADCx->CR1;
0002d0 6842 LDR r2,[r0,#4]
;;;1168 /* Clear AWDEN, AWDENJ and AWDSGL bits */
;;;1169 tmpreg &= CR1_AWDMode_Reset;
0002d2 4b21 LDR r3,|L1.856|
0002d4 401a ANDS r2,r2,r3
;;;1170 /* Set the analog watchdog enable mode */
;;;1171 tmpreg |= ADC_AnalogWatchdog;
0002d6 430a ORRS r2,r2,r1
;;;1172 /* Store the new register value */
;;;1173 ADCx->CR1 = tmpreg;
0002d8 6042 STR r2,[r0,#4]
;;;1174 }
0002da 4770 BX lr
;;;1175
ENDP
ADC_AnalogWatchdogThresholdsConfig PROC
;;;1195 /* Set the ADCx high threshold */
;;;1196 ADCx->HTR = HighThreshold;
0002dc 6241 STR r1,[r0,#0x24]
;;;1197 /* Set the ADCx low threshold */
;;;1198 ADCx->LTR = LowThreshold;
0002de 6282 STR r2,[r0,#0x28]
;;;1199 }
0002e0 4770 BX lr
;;;1200
ENDP
ADC_AnalogWatchdogSingleChannelConfig PROC
;;;1237 /* Get the old register value */
;;;1238 tmpreg = ADCx->CR1;
0002e2 6842 LDR r2,[r0,#4]
;;;1239 /* Clear the Analog watchdog channel select bits */
;;;1240 tmpreg &= CR1_AWDCH_Reset;
0002e4 f022f022 BIC r2,r2,#0x1f
;;;1241 /* Set the Analog watchdog channel */
;;;1242 tmpreg |= ADC_Channel;
0002e8 430a ORRS r2,r2,r1
;;;1243 /* Store the new register value */
;;;1244 ADCx->CR1 = tmpreg;
0002ea 6042 STR r2,[r0,#4]
;;;1245 }
0002ec 4770 BX lr
;;;1246
ENDP
ADC_TempSensorVrefintCmd PROC
;;;1259
;;;1260 if (NewState != DISABLE)
0002ee 491b LDR r1,|L1.860|
0002f0 b130 CBZ r0,|L1.768|
;;;1261 {
;;;1262 /* Enable the temperature sensor and Vrefint channel*/
;;;1263 ADC1->CR2 |= CR2_TSVREFE_Set;
0002f2 f8d1f8d1 LDR r0,[r1,#0x408]
0002f6 f440f440 ORR r0,r0,#0x800000
0002fa f8c1f8c1 STR r0,[r1,#0x408]
;;;1264 }
;;;1265 else
;;;1266 {
;;;1267 /* Disable the temperature sensor and Vrefint channel*/
;;;1268 ADC1->CR2 &= CR2_TSVREFE_Reset;
;;;1269 }
;;;1270 }
0002fe 4770 BX lr
|L1.768|
000300 f8d1f8d1 LDR r0,[r1,#0x408] ;1268
000304 f420f420 BIC r0,r0,#0x800000 ;1268
000308 f8c1f8c1 STR r0,[r1,#0x408] ;1268
00030c 4770 BX lr
;;;1271
ENDP
ADC_GetFlagStatus PROC
;;;1286 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG)
;;;1287 {
00030e 4602 MOV r2,r0
;;;1288 FlagStatus bitstatus = RESET;
000310 2000 MOVS r0,#0
;;;1289
;;;1290 /* Check the parameters */
;;;1291 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;1292 assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
;;;1293
;;;1294 /* Check the status of the specified ADC flag */
;;;1295 if ((ADCx->SR & ADC_FLAG) != (u8)RESET)
000312 6812 LDR r2,[r2,#0]
000314 420a TST r2,r1
000316 d000 BEQ |L1.794|
;;;1296 {
;;;1297 /* ADC_FLAG is set */
;;;1298 bitstatus = SET;
000318 2001 MOVS r0,#1
|L1.794|
;;;1299 }
;;;1300 else
;;;1301 {
;;;1302 /* ADC_FLAG is reset */
;;;1303 bitstatus = RESET;
;;;1304 }
;;;1305
;;;1306 /* Return the ADC_FLAG status */
;;;1307 return bitstatus;
;;;1308 }
00031a 4770 BX lr
;;;1309
ENDP
ADC_ClearFlag PROC
;;;1330 /* Clear the selected ADC flags */
;;;1331 ADCx->SR = ~(u32)ADC_FLAG;
00031c 43c9 MVNS r1,r1
00031e 6001 STR r1,[r0,#0]
;;;1332 }
000320 4770 BX lr
;;;1333
ENDP
ADC_GetITStatus PROC
;;;1346 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT)
;;;1347 {
000322 b510 PUSH {r4,lr}
000324 4602 MOV r2,r0
;;;1348 ITStatus bitstatus = RESET;
000326 2000 MOVS r0,#0
;;;1349 u32 itmask = 0, enablestatus = 0;
;;;1350
;;;1351 /* Check the parameters */
;;;1352 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;1353 assert_param(IS_ADC_GET_IT(ADC_IT));
;;;1354
;;;1355 /* Get the ADC IT index */
;;;1356 itmask = ADC_IT >> 8;
000328 0a0b LSRS r3,r1,#8
;;;1357
;;;1358 /* Get the ADC_IT enable bit status */
;;;1359 enablestatus = (ADCx->CR1 & (u8)ADC_IT) ;
00032a 6854 LDR r4,[r2,#4]
00032c b2c9 UXTB r1,r1
00032e 400c ANDS r4,r4,r1
;;;1360
;;;1361 /* Check the status of the specified ADC interrupt */
;;;1362 if (((ADCx->SR & itmask) != (u32)RESET) && enablestatus)
000330 6811 LDR r1,[r2,#0]
000332 4219 TST r1,r3
000334 d002 BEQ |L1.828|
000336 2c00 CMP r4,#0
000338 d000 BEQ |L1.828|
;;;1363 {
;;;1364 /* ADC_IT is set */
;;;1365 bitstatus = SET;
00033a 2001 MOVS r0,#1
|L1.828|
;;;1366 }
;;;1367 else
;;;1368 {
;;;1369 /* ADC_IT is reset */
;;;1370 bitstatus = RESET;
;;;1371 }
;;;1372
;;;1373 /* Return the ADC_IT status */
;;;1374 return bitstatus;
;;;1375 }
00033c bd10 POP {r4,pc}
;;;1376
ENDP
ADC_ClearITPendingBit PROC
;;;1397 /* Get the ADC IT index */
;;;1398 itmask = (u8)(ADC_IT >> 8);
00033e 0a09 LSRS r1,r1,#8
;;;1399
;;;1400 /* Clear the selected ADC interrupt pending bits */
;;;1401 ADCx->SR = ~(u32)itmask;
000340 43c9 MVNS r1,r1
000342 6001 STR r1,[r0,#0]
;;;1402 }
000344 4770 BX lr
;;;1403
ENDP
000346 0000 DCW 0x0000
|L1.840|
000348 bffedc00 DCD 0xbffedc00
|L1.844|
00034c fff0feff DCD 0xfff0feff
|L1.848|
000350 fff1f7fd DCD 0xfff1f7fd
|L1.852|
000354 4001244c DCD 0x4001244c
|L1.856|
000358 ff3ffdff DCD 0xff3ffdff
|L1.860|
00035c 40012000 DCD 0x40012000
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