📄 stm32f10x_adc.txt
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;;;380 /* Check the parameters */
;;;381 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;382
;;;383 /* Check the status of RSTCAL bit */
;;;384 if ((ADCx->CR2 & CR2_RSTCAL_Set) != (u32)RESET)
0000f6 6889 LDR r1,[r1,#8]
0000f8 0709 LSLS r1,r1,#28
0000fa d500 BPL |L1.254|
;;;385 {
;;;386 /* RSTCAL bit is set */
;;;387 bitstatus = SET;
0000fc 2001 MOVS r0,#1
|L1.254|
;;;388 }
;;;389 else
;;;390 {
;;;391 /* RSTCAL bit is reset */
;;;392 bitstatus = RESET;
;;;393 }
;;;394
;;;395 /* Return the RSTCAL bit status */
;;;396 return bitstatus;
;;;397 }
0000fe 4770 BX lr
;;;398
ENDP
ADC_StartCalibration PROC
;;;411 /* Enable the selected ADC calibration process */
;;;412 ADCx->CR2 |= CR2_CAL_Set;
000100 6881 LDR r1,[r0,#8]
000102 f041f041 ORR r1,r1,#4
000106 6081 STR r1,[r0,#8]
;;;413 }
000108 4770 BX lr
;;;414
ENDP
ADC_GetCalibrationStatus PROC
;;;422 FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
;;;423 {
00010a 4601 MOV r1,r0
;;;424 FlagStatus bitstatus = RESET;
00010c 2000 MOVS r0,#0
;;;425
;;;426 /* Check the parameters */
;;;427 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;428
;;;429 /* Check the status of CAL bit */
;;;430 if ((ADCx->CR2 & CR2_CAL_Set) != (u32)RESET)
00010e 6889 LDR r1,[r1,#8]
000110 0749 LSLS r1,r1,#29
000112 d500 BPL |L1.278|
;;;431 {
;;;432 /* CAL bit is set: calibration on going */
;;;433 bitstatus = SET;
000114 2001 MOVS r0,#1
|L1.278|
;;;434 }
;;;435 else
;;;436 {
;;;437 /* CAL bit is reset: end of calibration */
;;;438 bitstatus = RESET;
;;;439 }
;;;440
;;;441 /* Return the CAL bit status */
;;;442 return bitstatus;
;;;443 }
000116 4770 BX lr
;;;444
ENDP
ADC_SoftwareStartConvCmd PROC
;;;459
;;;460 if (NewState != DISABLE)
000118 b121 CBZ r1,|L1.292|
;;;461 {
;;;462 /* Enable the selected ADC conversion on external event and start the selected
;;;463 ADC conversion */
;;;464 ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set;
00011a 6881 LDR r1,[r0,#8]
00011c f441f441 ORR r1,r1,#0x500000
000120 6081 STR r1,[r0,#8]
;;;465 }
;;;466 else
;;;467 {
;;;468 /* Disable the selected ADC conversion on external event and stop the selected
;;;469 ADC conversion */
;;;470 ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset;
;;;471 }
;;;472 }
000122 4770 BX lr
|L1.292|
000124 6881 LDR r1,[r0,#8] ;470
000126 f421f421 BIC r1,r1,#0x500000 ;470
00012a 6081 STR r1,[r0,#8] ;470
00012c 4770 BX lr
;;;473
ENDP
ADC_GetSoftwareStartConvStatus PROC
;;;481 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
;;;482 {
00012e 4601 MOV r1,r0
;;;483 FlagStatus bitstatus = RESET;
000130 2000 MOVS r0,#0
;;;484
;;;485 /* Check the parameters */
;;;486 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;487
;;;488 /* Check the status of SWSTART bit */
;;;489 if ((ADCx->CR2 & CR2_SWSTART_Set) != (u32)RESET)
000132 6889 LDR r1,[r1,#8]
000134 0249 LSLS r1,r1,#9
000136 d500 BPL |L1.314|
;;;490 {
;;;491 /* SWSTART bit is set */
;;;492 bitstatus = SET;
000138 2001 MOVS r0,#1
|L1.314|
;;;493 }
;;;494 else
;;;495 {
;;;496 /* SWSTART bit is reset */
;;;497 bitstatus = RESET;
;;;498 }
;;;499
;;;500 /* Return the SWSTART bit status */
;;;501 return bitstatus;
;;;502 }
00013a 4770 BX lr
;;;503
ENDP
ADC_DiscModeChannelCountConfig PROC
;;;523 /* Get the old register value */
;;;524 tmpreg1 = ADCx->CR1;
00013c 6842 LDR r2,[r0,#4]
;;;525 /* Clear the old discontinuous mode channel count */
;;;526 tmpreg1 &= CR1_DISCNUM_Reset;
00013e f422f422 BIC r2,r2,#0xe000
;;;527 /* Set the discontinuous mode channel count */
;;;528 tmpreg2 = Number - 1;
000142 1e49 SUBS r1,r1,#1
;;;529 tmpreg1 |= tmpreg2 << 13;
000144 ea42ea42 ORR r1,r2,r1,LSL #13
;;;530 /* Store the new register value */
;;;531 ADCx->CR1 = tmpreg1;
000148 6041 STR r1,[r0,#4]
;;;532 }
00014a 4770 BX lr
;;;533
ENDP
ADC_DiscModeCmd PROC
;;;550
;;;551 if (NewState != DISABLE)
00014c b121 CBZ r1,|L1.344|
;;;552 {
;;;553 /* Enable the selected ADC regular discontinuous mode */
;;;554 ADCx->CR1 |= CR1_DISCEN_Set;
00014e 6841 LDR r1,[r0,#4]
000150 f441f441 ORR r1,r1,#0x800
000154 6041 STR r1,[r0,#4]
;;;555 }
;;;556 else
;;;557 {
;;;558 /* Disable the selected ADC regular discontinuous mode */
;;;559 ADCx->CR1 &= CR1_DISCEN_Reset;
;;;560 }
;;;561 }
000156 4770 BX lr
|L1.344|
000158 6841 LDR r1,[r0,#4] ;559
00015a f421f421 BIC r1,r1,#0x800 ;559
00015e 6041 STR r1,[r0,#4] ;559
000160 4770 BX lr
;;;562
ENDP
ADC_RegularChannelConfig PROC
;;;604 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime)
;;;605 {
000162 b570 PUSH {r4-r6,lr}
;;;606 u32 tmpreg1 = 0, tmpreg2 = 0;
;;;607
;;;608 /* Check the parameters */
;;;609 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;610 assert_param(IS_ADC_CHANNEL(ADC_Channel));
;;;611 assert_param(IS_ADC_REGULAR_RANK(Rank));
;;;612 assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
;;;613
;;;614 /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
;;;615 if (ADC_Channel > ADC_Channel_9)
000164 2607 MOVS r6,#7
000166 2909 CMP r1,#9
000168 d90a BLS |L1.384|
;;;616 {
;;;617 /* Get the old register value */
;;;618 tmpreg1 = ADCx->SMPR1;
00016a 68c5 LDR r5,[r0,#0xc]
;;;619 /* Calculate the mask to clear */
;;;620 tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
00016c f1a1f1a1 SUB r4,r1,#0xa
000170 eb04eb04 ADD r4,r4,r4,LSL #1
000174 40a6 LSLS r6,r6,r4
;;;621 /* Clear the old discontinuous mode channel count */
;;;622 tmpreg1 &= ~tmpreg2;
000176 43b5 BICS r5,r5,r6
;;;623 /* Calculate the mask to set */
;;;624 tmpreg2 = (u32)ADC_SampleTime << (3 * (ADC_Channel - 10));
000178 40a3 LSLS r3,r3,r4
;;;625 /* Set the discontinuous mode channel count */
;;;626 tmpreg1 |= tmpreg2;
00017a 431d ORRS r5,r5,r3
;;;627 /* Store the new register value */
;;;628 ADCx->SMPR1 = tmpreg1;
00017c 60c5 STR r5,[r0,#0xc]
00017e e007 B |L1.400|
|L1.384|
;;;629 }
;;;630 else /* ADC_Channel include in ADC_Channel_[0..9] */
;;;631 {
;;;632 /* Get the old register value */
;;;633 tmpreg1 = ADCx->SMPR2;
000180 6905 LDR r5,[r0,#0x10]
;;;634 /* Calculate the mask to clear */
;;;635 tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
000182 eb01eb01 ADD r4,r1,r1,LSL #1
000186 40a6 LSLS r6,r6,r4
;;;636 /* Clear the old discontinuous mode channel count */
;;;637 tmpreg1 &= ~tmpreg2;
000188 43b5 BICS r5,r5,r6
;;;638 /* Calculate the mask to set */
;;;639 tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);
00018a 40a3 LSLS r3,r3,r4
;;;640 /* Set the discontinuous mode channel count */
;;;641 tmpreg1 |= tmpreg2;
00018c 431d ORRS r5,r5,r3
;;;642 /* Store the new register value */
;;;643 ADCx->SMPR2 = tmpreg1;
00018e 6105 STR r5,[r0,#0x10]
|L1.400|
;;;644 }
;;;645 /* For Rank 1 to 6 */
;;;646 if (Rank < 7)
000190 231f MOVS r3,#0x1f
000192 2a07 CMP r2,#7
000194 d209 BCS |L1.426|
;;;647 {
;;;648 /* Get the old register value */
;;;649 tmpreg1 = ADCx->SQR3;
000196 6b44 LDR r4,[r0,#0x34]
;;;650 /* Calculate the mask to clear */
;;;651 tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));
000198 1e52 SUBS r2,r2,#1
00019a eb02eb02 ADD r2,r2,r2,LSL #2
00019e 4093 LSLS r3,r3,r2
;;;652 /* Clear the old SQx bits for the selected rank */
;;;653 tmpreg1 &= ~tmpreg2;
0001a0 439c BICS r4,r4,r3
;;;654 /* Calculate the mask to set */
;;;655 tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 1));
0001a2 4091 LSLS r1,r1,r2
;;;656 /* Set the SQx bits for the selected rank */
;;;657 tmpreg1 |= tmpreg2;
0001a4 430c ORRS r4,r4,r1
;;;658 /* Store the new register value */
;;;659 ADCx->SQR3 = tmpreg1;
0001a6 6344 STR r4,[r0,#0x34]
;;;660 }
;;;661 /* For Rank 7 to 12 */
;;;662 else if (Rank < 13)
;;;663 {
;;;664 /* Get the old register value */
;;;665 tmpreg1 = ADCx->SQR2;
;;;666 /* Calculate the mask to clear */
;;;667 tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));
;;;668 /* Clear the old SQx bits for the selected rank */
;;;669 tmpreg1 &= ~tmpreg2;
;;;670 /* Calculate the mask to set */
;;;671 tmpreg2 = (u32)ADC_Channel << (5 * (Rank - 7));
;;;672 /* Set the SQx bits for the selected rank */
;;;673 tmpreg1 |= tmpreg2;
;;;674 /* Store the new register value */
;;;675 ADCx->SQR2 = tmpreg1;
;;;676 }
;;;677 /* For Rank 13 to 16 */
;;;678 else
;;;679 {
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