📄 stm32f10x_gpio.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 919] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\output\stm32f10x_gpio.o --depend=.\output\stm32f10x_gpio.d --device=DARMSTM --apcs=interwork -O1 -I. -I..\BSP -I..\..\..\..\..\uCOS-II\Ports\arm-cortex-m3\Generic\RealView -I..\..\..\..\..\uCOS-II\Source -I..\..\..\..\..\CPU\ST\STM32\inc -I..\..\..\..\..\uC-CPU -I..\..\..\..\..\uC-CPU\Arm-Cortex-M3\RealView -I..\..\..\..\..\uC-LIB -IC:\Keil\ARM\INC\ST\STM32F10x --omf_browse=.\output\stm32f10x_gpio.crf ..\..\..\..\..\CPU\ST\STM32\src\stm32f10x_gpio.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
GPIO_DeInit PROC
;;;53 void GPIO_DeInit(GPIO_TypeDef* GPIOx)
;;;54 {
000000 b510 PUSH {r4,lr}
;;;55 /* Check the parameters */
;;;56 assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
;;;57
;;;58 switch (*(u32*)&GPIOx)
000002 4a94 LDR r2,|L1.596|
000004 1a81 SUBS r1,r0,r2
000006 1513 ASRS r3,r2,#20
000008 14d4 ASRS r4,r2,#19
00000a 4290 CMP r0,r2
00000c d037 BEQ |L1.126|
00000e dc10 BGT |L1.50|
000010 4991 LDR r1,|L1.600|
000012 1840 ADDS r0,r0,r1
000014 d01f BEQ |L1.86|
000016 4298 CMP r0,r3
000018 d027 BEQ |L1.106|
00001a 42a0 CMP r0,r4
00001c d14d BNE |L1.186|
;;;59 {
;;;60 case GPIOA_BASE:
;;;61 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
;;;62 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
;;;63 break;
;;;64
;;;65 case GPIOB_BASE:
;;;66 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
;;;67 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
;;;68 break;
;;;69
;;;70 case GPIOC_BASE:
;;;71 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
00001e 2101 MOVS r1,#1
000020 2010 MOVS r0,#0x10
000022 f7fff7ff BL RCC_APB2PeriphResetCmd
;;;72 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
000026 2100 MOVS r1,#0
000028 e8bde8bd POP {r4,lr}
00002c 2010 MOVS r0,#0x10
00002e f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.50|
000032 4299 CMP r1,r3 ;58
000034 d02d BEQ |L1.146|
000036 42a1 CMP r1,r4 ;58
000038 d035 BEQ |L1.166|
00003a f5b1f5b1 CMP r1,#0xc00 ;58
00003e d13c BNE |L1.186|
;;;73 break;
;;;74
;;;75 case GPIOD_BASE:
;;;76 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
;;;77 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
;;;78 break;
;;;79
;;;80 case GPIOE_BASE:
;;;81 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
;;;82 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
;;;83 break;
;;;84
;;;85 case GPIOF_BASE:
;;;86 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
;;;87 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
;;;88 break;
;;;89
;;;90 case GPIOG_BASE:
;;;91 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
000040 2101 MOVS r1,#1
000042 020c LSLS r4,r1,#8
000044 4620 MOV r0,r4
000046 f7fff7ff BL RCC_APB2PeriphResetCmd
;;;92 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
00004a 4620 MOV r0,r4
00004c e8bde8bd POP {r4,lr}
000050 2100 MOVS r1,#0
000052 f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.86|
000056 2101 MOVS r1,#1 ;61
000058 2004 MOVS r0,#4 ;61
00005a f7fff7ff BL RCC_APB2PeriphResetCmd
00005e 2100 MOVS r1,#0 ;62
000060 e8bde8bd POP {r4,lr} ;62
000064 2004 MOVS r0,#4 ;62
000066 f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.106|
00006a 2101 MOVS r1,#1 ;66
00006c 2008 MOVS r0,#8 ;66
00006e f7fff7ff BL RCC_APB2PeriphResetCmd
000072 2100 MOVS r1,#0 ;67
000074 e8bde8bd POP {r4,lr} ;67
000078 2008 MOVS r0,#8 ;67
00007a f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.126|
00007e 2101 MOVS r1,#1 ;76
000080 2020 MOVS r0,#0x20 ;76
000082 f7fff7ff BL RCC_APB2PeriphResetCmd
000086 2100 MOVS r1,#0 ;77
000088 e8bde8bd POP {r4,lr} ;77
00008c 2020 MOVS r0,#0x20 ;77
00008e f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.146|
000092 2101 MOVS r1,#1 ;81
000094 2040 MOVS r0,#0x40 ;81
000096 f7fff7ff BL RCC_APB2PeriphResetCmd
00009a 2100 MOVS r1,#0 ;82
00009c e8bde8bd POP {r4,lr} ;82
0000a0 2040 MOVS r0,#0x40 ;82
0000a2 f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.166|
0000a6 2101 MOVS r1,#1 ;86
0000a8 2080 MOVS r0,#0x80 ;86
0000aa f7fff7ff BL RCC_APB2PeriphResetCmd
0000ae 2100 MOVS r1,#0 ;87
0000b0 e8bde8bd POP {r4,lr} ;87
0000b4 2080 MOVS r0,#0x80 ;87
0000b6 f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.186|
;;;93 break;
;;;94
;;;95 default:
;;;96 break;
;;;97 }
;;;98 }
0000ba bd10 POP {r4,pc}
;;;99
ENDP
GPIO_AFIODeInit PROC
;;;109 void GPIO_AFIODeInit(void)
;;;110 {
0000bc b510 PUSH {r4,lr}
;;;111 RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
0000be 2101 MOVS r1,#1
0000c0 4608 MOV r0,r1
0000c2 f7fff7ff BL RCC_APB2PeriphResetCmd
;;;112 RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
0000c6 2100 MOVS r1,#0
0000c8 e8bde8bd POP {r4,lr}
0000cc 2001 MOVS r0,#1
0000ce f7fff7ff B.W RCC_APB2PeriphResetCmd
;;;113 }
;;;114
ENDP
GPIO_Init PROC
;;;126 void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
;;;127 {
0000d2 b5f0 PUSH {r4-r7,lr}
;;;128 u32 currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
0000d4 2200 MOVS r2,#0
;;;129 u32 tmpreg = 0x00, pinmask = 0x00;
;;;130
;;;131 /* Check the parameters */
;;;132 assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
;;;133 assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
;;;134 assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
;;;135
;;;136 /*---------------------------- GPIO Mode Configuration -----------------------*/
;;;137 currentmode = ((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x0F);
0000d6 78cc LDRB r4,[r1,#3]
0000d8 f004f004 AND r3,r4,#0xf
;;;138
;;;139 if ((((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x10)) != 0x00)
0000dc 06e4 LSLS r4,r4,#27
0000de d501 BPL |L1.228|
;;;140 {
;;;141 /* Check the parameters */
;;;142 assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
;;;143 /* Output mode */
;;;144 currentmode |= (u32)GPIO_InitStruct->GPIO_Speed;
0000e0 788c LDRB r4,[r1,#2]
0000e2 4323 ORRS r3,r3,r4
|L1.228|
;;;145 }
;;;146
;;;147 /*---------------------------- GPIO CRL Configuration ------------------------*/
;;;148 /* Configure the eight low port pins */
;;;149 if (((u32)GPIO_InitStruct->GPIO_Pin & ((u32)0x00FF)) != 0x00)
0000e4 880c LDRH r4,[r1,#0]
0000e6 f04ff04f MOV r7,#0xf
0000ea f014f014 TST r4,#0xff
0000ee f04ff04f MOV r12,#1
0000f2 d01b BEQ |L1.300|
;;;150 {
;;;151 tmpreg = GPIOx->CRL;
0000f4 6805 LDR r5,[r0,#0]
|L1.246|
;;;152
;;;153 for (pinpos = 0x00; pinpos < 0x08; pinpos++)
;;;154 {
;;;155 pos = ((u32)0x01) << pinpos;
0000f6 fa0cfa0c LSL r4,r12,r2
;;;156 /* Get the port pins position */
;;;157 currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
0000fa 880e LDRH r6,[r1,#0]
0000fc 4026 ANDS r6,r6,r4
;;;158
;;;159 if (currentpin == pos)
0000fe 42a6 CMP r6,r4
000100 d110 BNE |L1.292|
;;;160 {
;;;161 pos = pinpos << 2;
000102 0096 LSLS r6,r2,#2
;;;162 /* Clear the corresponding low control register bits */
;;;163 pinmask = ((u32)0x0F) << pos;
000104 fa07fa07 LSL lr,r7,r6
;;;164 tmpreg &= ~pinmask;
000108 ea25ea25 BIC lr,r5,lr
;;;165
;;;166 /* Write the mode configuration in the corresponding bits */
;;;167 tmpreg |= (currentmode << pos);
00010c fa03fa03 LSL r5,r3,r6
000110 ea45ea45 ORR r5,r5,lr
;;;168
;;;169 /* Reset the corresponding ODR bit */
;;;170 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
000114 78ce LDRB r6,[r1,#3]
000116 2e28 CMP r6,#0x28
000118 d100 BNE |L1.284|
;;;171 {
;;;172 GPIOx->BRR = (((u32)0x01) << pinpos);
00011a 6144 STR r4,[r0,#0x14]
|L1.284|
;;;173 }
;;;174 /* Set the corresponding ODR bit */
;;;175 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
00011c 78ce LDRB r6,[r1,#3]
00011e 2e48 CMP r6,#0x48
000120 d100 BNE |L1.292|
;;;176 {
;;;177 GPIOx->BSRR = (((u32)0x01) << pinpos);
000122 6104 STR r4,[r0,#0x10]
|L1.292|
000124 1c52 ADDS r2,r2,#1 ;153
000126 2a08 CMP r2,#8 ;153
000128 d3e5 BCC |L1.246|
;;;178 }
;;;179 }
;;;180 }
;;;181 GPIOx->CRL = tmpreg;
00012a 6005 STR r5,[r0,#0]
|L1.300|
;;;182 }
;;;183
;;;184 /*---------------------------- GPIO CRH Configuration ------------------------*/
;;;185 /* Configure the eight high port pins */
;;;186 if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
00012c 880a LDRH r2,[r1,#0]
00012e 2aff CMP r2,#0xff
000130 d91e BLS |L1.368|
;;;187 {
;;;188 tmpreg = GPIOx->CRH;
000132 6845 LDR r5,[r0,#4]
;;;189 for (pinpos = 0x00; pinpos < 0x08; pinpos++)
000134 2200 MOVS r2,#0
|L1.310|
;;;190 {
;;;191 pos = (((u32)0x01) << (pinpos + 0x08));
000136 f102f102 ADD r6,r2,#8
00013a fa0cfa0c LSL r4,r12,r6
;;;192 /* Get the port pins position */
;;;193 currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
00013e 880e LDRH r6,[r1,#0]
000140 4026 ANDS r6,r6,r4
;;;194 if (currentpin == pos)
000142 42a6 CMP r6,r4
000144 d110 BNE |L1.360|
;;;195 {
;;;196 pos = pinpos << 2;
000146 0096 LSLS r6,r2,#2
;;;197 /* Clear the corresponding high control register bits */
;;;198 pinmask = ((u32)0x0F) << pos;
000148 fa07fa07 LSL lr,r7,r6
;;;199 tmpreg &= ~pinmask;
00014c ea25ea25 BIC lr,r5,lr
;;;200
;;;201 /* Write the mode configuration in the corresponding bits */
;;;202 tmpreg |= (currentmode << pos);
000150 fa03fa03 LSL r5,r3,r6
000154 ea45ea45 ORR r5,r5,lr
;;;203
;;;204 /* Reset the corresponding ODR bit */
;;;205 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
000158 78ce LDRB r6,[r1,#3]
00015a 2e28 CMP r6,#0x28
00015c d100 BNE |L1.352|
;;;206 {
;;;207 GPIOx->BRR = (((u32)0x01) << (pinpos + 0x08));
00015e 6144 STR r4,[r0,#0x14]
|L1.352|
;;;208 }
;;;209 /* Set the corresponding ODR bit */
;;;210 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
000160 78ce LDRB r6,[r1,#3]
000162 2e48 CMP r6,#0x48
000164 d100 BNE |L1.360|
;;;211 {
;;;212 GPIOx->BSRR = (((u32)0x01) << (pinpos + 0x08));
000166 6104 STR r4,[r0,#0x10]
|L1.360|
000168 1c52 ADDS r2,r2,#1 ;189
00016a 2a08 CMP r2,#8 ;189
00016c d3e3 BCC |L1.310|
;;;213 }
;;;214 }
;;;215 }
;;;216 GPIOx->CRH = tmpreg;
00016e 6045 STR r5,[r0,#4]
|L1.368|
;;;217 }
;;;218 }
000170 bdf0 POP {r4-r7,pc}
;;;219
ENDP
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