📄 cpu_a.lst
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ARM Macro Assembler Page 1
1 00000000 ;*******************************************************
*************************************************
2 00000000 ; uC/CPU
3 00000000 ; CPU CONFIGURATION &
PORT LAYER
4 00000000 ;
5 00000000 ; (c) Copyright 2004-2008; Micr
ium, Inc.; Weston, FL
6 00000000 ;
7 00000000 ; All rights reserved. Protected by inter
national copyright laws.
8 00000000 ;
9 00000000 ; uC/CPU is provided in source form for FR
EE evaluation, for educational
10 00000000 ; use or peaceful research. If you plan o
n using uC/CPU in a commercial
11 00000000 ; product you need to contact Micrium to p
roperly license its use in your
12 00000000 ; product. We provide ALL the source code
for your convenience and to
13 00000000 ; help you experience uC/CPU. The fact th
at the source code is provided
14 00000000 ; does NOT mean that you can use it withou
t paying a licensing fee.
15 00000000 ;
16 00000000 ; Knowledge of the source code may NOT be
used to develop a similar product.
17 00000000 ;
18 00000000 ; Please help us continue to provide the E
mbedded community with the finest
19 00000000 ; software available. Your honesty is gre
atly appreciated.
20 00000000 ;*******************************************************
*************************************************
21 00000000
22 00000000
23 00000000 ;*******************************************************
*************************************************
24 00000000 ;
25 00000000 ; CPU PORT FI
LE
26 00000000 ;
27 00000000 ; ARM-Cortex-
M3
28 00000000 ; RealView Developm
ent Suite
29 00000000 ; RealView Microcontroller De
velopment Kit (MDK)
30 00000000 ; ARM Developer Su
ite (ADS)
31 00000000 ; Keil uVisio
n
32 00000000 ;
33 00000000 ; Filename : cpu_a.asm
34 00000000 ; Version : V1.19
35 00000000 ; Programmer(s) : BAN
36 00000000 ;*******************************************************
*************************************************
37 00000000
ARM Macro Assembler Page 2
38 00000000
39 00000000 ;*******************************************************
*************************************************
40 00000000 ; PUBLIC FUNCT
IONS
41 00000000 ;*******************************************************
*************************************************
42 00000000
43 00000000 EXPORT CPU_IntDis
44 00000000 EXPORT CPU_IntEn
45 00000000
46 00000000 EXPORT CPU_SR_Save
47 00000000 EXPORT CPU_SR_Restore
48 00000000
49 00000000 EXPORT CPU_CntLeadZeros
50 00000000 EXPORT CPU_RevBits
51 00000000
52 00000000 EXPORT CPU_WaitForInt
53 00000000 EXPORT CPU_WaitForExcept
54 00000000
55 00000000
56 00000000 ;*******************************************************
*************************************************
57 00000000 ; CODE GENERATION D
IRECTIVES
58 00000000 ;*******************************************************
*************************************************
59 00000000
60 00000000 AREA |.text|, CODE, READONLY, ALIGN=
2
61 00000000 THUMB
62 00000000 REQUIRE8
63 00000000 PRESERVE8
64 00000000
65 00000000
66 00000000 ;$PAGE
67 00000000 ;*******************************************************
**************************************************
68 00000000 ; DISABLE and ENABLE
INTERRUPTS
69 00000000 ;
70 00000000 ; Description : Disable/Enable interrupts.
71 00000000 ;
72 00000000 ; Prototypes : void CPU_IntDis(void);
73 00000000 ; void CPU_IntEn (void);
74 00000000 ;*******************************************************
**************************************************
75 00000000
76 00000000 CPU_IntDis
77 00000000 B672 CPSID I
78 00000002 4770 BX LR
79 00000004
80 00000004
81 00000004 CPU_IntEn
82 00000004 B662 CPSIE I
83 00000006 4770 BX LR
84 00000008
85 00000008
86 00000008 ;*******************************************************
ARM Macro Assembler Page 3
**************************************************
87 00000008 ; CRITICAL SECTION
FUNCTIONS
88 00000008 ;
89 00000008 ; Description : Disable/Enable interrupts by preserving
the state of interrupts. Generally speaking, the
90 00000008 ; state of the interrupt disable flag is s
tored in the local variable 'cpu_sr' & interrupts
91 00000008 ; are then disabled ('cpu_sr' is allocated
in all functions that need to disable interrupts).
92 00000008 ; The previous interrupt state is restored
by copying 'cpu_sr' into the CPU's status register.
93 00000008 ;
94 00000008 ; Prototypes : CPU_SR CPU_SR_Save (void);
95 00000008 ; void CPU_SR_Restore(CPU_SR cpu_sr);
96 00000008 ;
97 00000008 ;
98 00000008 ; Note(s) : (1) These functions are used in general
like this:
99 00000008 ;
100 00000008 ; void Task (void *p_arg)
101 00000008 ; {
102 00000008 ;
/* Allocate storage for CPU status register */
103 00000008 ; #if (CPU_CFG_CRITICAL_METHOD == CPU_
CRITICAL_METHOD_STATUS_LOCAL)
104 00000008 ; CPU_SR cpu_sr;
105 00000008 ; #endif
106 00000008 ;
107 00000008 ; :
108 00000008 ; :
109 00000008 ; CPU_CRITICAL_ENTER();
/* cpu_sr = CPU_SR_Save(); */
110 00000008 ; :
111 00000008 ; :
112 00000008 ; CPU_CRITICAL_EXIT();
/* CPU_SR_Restore(cpu_sr); */
113 00000008 ; :
114 00000008 ; :
115 00000008 ; }
116 00000008 ;*******************************************************
**************************************************
117 00000008
118 00000008 CPU_SR_Save
119 00000008 F3EF 8010 MRS R0, PRIMASK ; Set prio int mask
to mask all (excep
t faults)
120 0000000C B672 CPSID I
121 0000000E 4770 BX LR
122 00000010
123 00000010
124 00000010 CPU_SR_Restore ; See Note #2.
125 00000010 F380 8810 MSR PRIMASK, R0
126 00000014 4770 BX LR
127 00000016
128 00000016
129 00000016 ;$PAGE
130 00000016 ;*******************************************************
*************************************************
ARM Macro Assembler Page 4
131 00000016 ; COUNT LEADING
ZEROS
132 00000016 ;
133 00000016 ; Description : Counts the number of binary zero bits be
fore the first binary one bit in the argument.
134 00000016 ; If the argument is zero, the value 32 is
returned.
135 00000016 ;
136 00000016 ; Prototypes : CPU_INT32U CPU_CntLeadZeros (CPU_INT32U
val)
137 00000016 ;
138 00000016 ; Argument(s) : val variable to count leading zeros
139 00000016 ;*******************************************************
*************************************************
140 00000016
141 00000016 CPU_CntLeadZeros
142 00000016 FAB0 F080 CLZ R0, R0 ; Count leading zer
os
143 0000001A 4770 BX LR
144 0000001C
145 0000001C
146 0000001C ;*******************************************************
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