cpu.h

stm32 ucos 精简移殖版本 不需作任何修改直接便可运行。包含串口 定时器

#define  CPU_REG_DBG_DATA               (*((volatile CPU_INT32U *)(0xE000EDF8))) /* Debug Core Reg Data     Reg.        */
#define  CPU_REG_DBG_INT                (*((volatile CPU_INT32U *)(0xE000EDFC))) /* Debug Except & Monitor Ctrl Reg.    */

/*
*********************************************************************************************************
*                                          CPU REGISTER BITS
*********************************************************************************************************
*/

                                                                /* ---------- SYSTICK CTRL & STATUS REG BITS ---------- */
#define  CPU_REG_NVIC_ST_CTRL_COUNTFLAG         DEF_BIT_16
#define  CPU_REG_NVIC_ST_CTRL_CLKSOURCE         DEF_BIT_02
#define  CPU_REG_NVIC_ST_CTRL_TICKINT           DEF_BIT_01
#define  CPU_REG_NVIC_ST_CTRL_ENABLE            DEF_BIT_00


                                                                /* -------- SYSTICK CALIBRATION VALUE REG BITS -------- */
#define  CPU_REG_NVIC_ST_CAL_NOREF              DEF_BIT_31
#define  CPU_REG_NVIC_ST_CAL_SKEW               DEF_BIT_30

                                                                /* -------------- INT CTRL STATE REG BITS ------------- */
#define  CPU_REG_NVIC_ICSR_NMIPENDSET           DEF_BIT_31
#define  CPU_REG_NVIC_ICSR_PENDSVSET            DEF_BIT_28
#define  CPU_REG_NVIC_ICSR_PENDSVCLR            DEF_BIT_27
#define  CPU_REG_NVIC_ICSR_PENDSTSET            DEF_BIT_26
#define  CPU_REG_NVIC_ICSR_PENDSTCLR            DEF_BIT_25
#define  CPU_REG_NVIC_ICSR_ISRPREEMPT           DEF_BIT_23
#define  CPU_REG_NVIC_ICSR_ISRPENDING           DEF_BIT_22
#define  CPU_REG_NVIC_ICSR_RETTOBASE            DEF_BIT_11

                                                                /* ------------- VECT TBL OFFSET REG BITS ------------- */
#define  CPU_REG_NVIC_VTOR_TBLBASE              DEF_BIT_29

                                                                /* ------------ APP INT/RESET CTRL REG BITS ----------- */
#define  CPU_REG_NVIC_AIRCR_ENDIANNESS          DEF_BIT_15
#define  CPU_REG_NVIC_AIRCR_SYSRESETREQ         DEF_BIT_02
#define  CPU_REG_NVIC_AIRCR_VECTCLRACTIVE       DEF_BIT_01
#define  CPU_REG_NVIC_AIRCR_VECTRESET           DEF_BIT_00

                                                                /* --------------- SYSTEM CTRL REG BITS --------------- */
#define  CPU_REG_NVIC_SCR_SEVONPEND             DEF_BIT_04
#define  CPU_REG_NVIC_SCR_SLEEPDEEP             DEF_BIT_02
#define  CPU_REG_NVIC_SCR_SLEEPONEXIT           DEF_BIT_01

                                                                /* ----------------- CFG CTRL REG BITS ---------------- */
#define  CPU_REG_NVIC_CCR_STKALIGN              DEF_BIT_09
#define  CPU_REG_NVIC_CCR_BFHFNMIGN             DEF_BIT_08
#define  CPU_REG_NVIC_CCR_DIV_0_TRP             DEF_BIT_04
#define  CPU_REG_NVIC_CCR_UNALIGN_TRP           DEF_BIT_03
#define  CPU_REG_NVIC_CCR_USERSETMPEND          DEF_BIT_01
#define  CPU_REG_NVIC_CCR_NONBASETHRDENA        DEF_BIT_00

                                                                /* ------- SYSTEM HANDLER CTRL & STATE REG BITS ------- */
#define  CPU_REG_NVIC_SHCSR_USGFAULTENA         DEF_BIT_18
#define  CPU_REG_NVIC_SHCSR_BUSFAULTENA         DEF_BIT_17
#define  CPU_REG_NVIC_SHCSR_MEMFAULTENA         DEF_BIT_16
#define  CPU_REG_NVIC_SHCSR_SVCALLPENDED        DEF_BIT_15
#define  CPU_REG_NVIC_SHCSR_BUSFAULTPENDED      DEF_BIT_14
#define  CPU_REG_NVIC_SHCSR_MEMFAULTPENDED      DEF_BIT_13
#define  CPU_REG_NVIC_SHCSR_USGFAULTPENDED      DEF_BIT_12
#define  CPU_REG_NVIC_SHCSR_SYSTICKACT          DEF_BIT_11
#define  CPU_REG_NVIC_SHCSR_PENDSVACT           DEF_BIT_10
#define  CPU_REG_NVIC_SHCSR_MONITORACT          DEF_BIT_08
#define  CPU_REG_NVIC_SHCSR_SVCALLACT           DEF_BIT_07
#define  CPU_REG_NVIC_SHCSR_USGFAULTACT         DEF_BIT_03
#define  CPU_REG_NVIC_SHCSR_BUSFAULTACT         DEF_BIT_01
#define  CPU_REG_NVIC_SHCSR_MEMFAULTACT         DEF_BIT_00

                                                                /* -------- CONFIGURABLE FAULT STATUS REG BITS -------- */
#define  CPU_REG_NVIC_CFSR_DIVBYZERO            DEF_BIT_25
#define  CPU_REG_NVIC_CFSR_UNALIGNED            DEF_BIT_24
#define  CPU_REG_NVIC_CFSR_NOCP                 DEF_BIT_19
#define  CPU_REG_NVIC_CFSR_INVPC                DEF_BIT_18
#define  CPU_REG_NVIC_CFSR_INVSTATE             DEF_BIT_17
#define  CPU_REG_NVIC_CFSR_UNDEFINSTR           DEF_BIT_16
#define  CPU_REG_NVIC_CFSR_BFARVALID            DEF_BIT_15
#define  CPU_REG_NVIC_CFSR_STKERR               DEF_BIT_12
#define  CPU_REG_NVIC_CFSR_UNSTKERR             DEF_BIT_11
#define  CPU_REG_NVIC_CFSR_IMPRECISERR          DEF_BIT_10
#define  CPU_REG_NVIC_CFSR_PRECISERR            DEF_BIT_09
#define  CPU_REG_NVIC_CFSR_IBUSERR              DEF_BIT_08
#define  CPU_REG_NVIC_CFSR_MMARVALID            DEF_BIT_07
#define  CPU_REG_NVIC_CFSR_MSTKERR              DEF_BIT_04
#define  CPU_REG_NVIC_CFSR_MUNSTKERR            DEF_BIT_03
#define  CPU_REG_NVIC_CFSR_DACCVIOL             DEF_BIT_01
#define  CPU_REG_NVIC_CFSR_IACCVIOL             DEF_BIT_00

                                                                /* ------------ HARD FAULT STATUS REG BITS ------------ */
#define  CPU_REG_NVIC_HFSR_DEBUGEVT             DEF_BIT_31
#define  CPU_REG_NVIC_HFSR_FORCED               DEF_BIT_30
#define  CPU_REG_NVIC_HFSR_VECTTBL              DEF_BIT_01

                                                                /* ------------ DEBUG FAULT STATUS REG BITS ----------- */
#define  CPU_REG_NVIC_DFSR_EXTERNAL             DEF_BIT_04
#define  CPU_REG_NVIC_DFSR_VCATCH               DEF_BIT_03
#define  CPU_REG_NVIC_DFSR_DWTTRAP              DEF_BIT_02
#define  CPU_REG_NVIC_DFSR_BKPT                 DEF_BIT_01
#define  CPU_REG_NVIC_DFSR_HALTED               DEF_BIT_00

/*$PAGE*/
/*
*********************************************************************************************************
*                                        CONFIGURATION ERRORS
*********************************************************************************************************
*/

#ifndef   CPU_CFG_ADDR_SIZE
#error   "CPU_CFG_ADDR_SIZE              not #define'd in 'cpu.h'               "
#error   "                         [MUST be  CPU_WORD_SIZE_08   8-bit alignment]"
#error   "                         [     ||  CPU_WORD_SIZE_16  16-bit alignment]"
#error   "                         [     ||  CPU_WORD_SIZE_32  32-bit alignment]"

#elif   ((CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_08) && \
         (CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_16) && \
         (CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_32))
#error   "CPU_CFG_ADDR_SIZE        illegally #define'd in 'cpu.h'               "
#error   "                         [MUST be  CPU_WORD_SIZE_08   8-bit alignment]"
#error   "                         [     ||  CPU_WORD_SIZE_16  16-bit alignment]"
#error   "                         [     ||  CPU_WORD_SIZE_32  32-bit alignment]"
#endif


#ifndef   CPU_CFG_DATA_SIZE
#error   "CPU_CFG_DATA_SIZE              not #define'd in 'cpu.h'               "
#error   "                         [MUST be  CPU_WORD_SIZE_08   8-bit alignment]"
#error   "                         [     ||  CPU_WORD_SIZE_16  16-bit alignment]"
#error   "                         [     ||  CPU_WORD_SIZE_32  32-bit alignment]"

#elif   ((CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_08) && \
         (CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_16) && \
         (CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_32))
#error   "CPU_CFG_DATA_SIZE        illegally #define'd in 'cpu.h'               "
#error   "                         [MUST be  CPU_WORD_SIZE_08   8-bit alignment]"
#error   "                         [     ||  CPU_WORD_SIZE_16  16-bit alignment]"
#error   "                         [     ||  CPU_WORD_SIZE_32  32-bit alignment]"
#endif



#ifndef   CPU_CFG_ENDIAN_TYPE
#error   "CPU_CFG_ENDIAN_TYPE            not #define'd in 'cpu.h'   "
#error   "                         [MUST be  CPU_ENDIAN_TYPE_BIG   ]"
#error   "                         [     ||  CPU_ENDIAN_TYPE_LITTLE]"

#elif   ((CPU_CFG_ENDIAN_TYPE != CPU_ENDIAN_TYPE_BIG   ) && \
         (CPU_CFG_ENDIAN_TYPE != CPU_ENDIAN_TYPE_LITTLE))
#error   "CPU_CFG_ENDIAN_TYPE      illegally #define'd in 'cpu.h'   "
#error   "                         [MUST be  CPU_ENDIAN_TYPE_BIG   ]"
#error   "                         [     ||  CPU_ENDIAN_TYPE_LITTLE]"
#endif




#ifndef   CPU_CFG_CRITICAL_METHOD
#error   "CPU_CFG_CRITICAL_METHOD        not #define'd in 'cpu.h'             "
#error   "                         [MUST be  CPU_CRITICAL_METHOD_INT_DIS_EN  ]"
#error   "                         [     ||  CPU_CRITICAL_METHOD_STATUS_STK  ]"
#error   "                         [     ||  CPU_CRITICAL_METHOD_STATUS_LOCAL]"

#elif   ((CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_INT_DIS_EN  ) && \
         (CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_STATUS_STK  ) && \
         (CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_STATUS_LOCAL))
#error   "CPU_CFG_CRITICAL_METHOD  illegally #define'd in 'cpu.h'             "
#error   "                         [MUST be  CPU_CRITICAL_METHOD_INT_DIS_EN  ]"
#error   "                         [     ||  CPU_CRITICAL_METHOD_STATUS_STK  ]"
#error   "                         [     ||  CPU_CRITICAL_METHOD_STATUS_LOCAL]"
#endif


/*$PAGE*/
/*
*********************************************************************************************************
*                                             MODULE END
*********************************************************************************************************
*/

#endif                                                          /* End of CPU cfg module inclusion.                     */