📄 cpu.h
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typedef CPU_DATA CPU_SIZE_T; /* Defines CPU standard 'size_t' size. */
/*$PAGE*/
/*
*********************************************************************************************************
* CRITICAL SECTION CONFIGURATION
*
* Note(s) : (1) Configure CPU_CFG_CRITICAL_METHOD with CPU's/compiler's critical section method :
*
* Enter/Exit critical sections by ...
*
* CPU_CRITICAL_METHOD_INT_DIS_EN Disable/Enable interrupts
* CPU_CRITICAL_METHOD_STATUS_STK Push/Pop interrupt status onto stack
* CPU_CRITICAL_METHOD_STATUS_LOCAL Save/Restore interrupt status to local variable
*
* (a) CPU_CRITICAL_METHOD_INT_DIS_EN is NOT a preferred method since it does NOT support
* multiple levels of interrupts. However, with some CPUs/compilers, this is the only
* available method.
*
* (b) CPU_CRITICAL_METHOD_STATUS_STK is one preferred method since it DOES support multiple
* levels of interrupts. However, this method assumes that the compiler allows in-line
* assembly AND will correctly modify the local stack pointer when interrupt status is
* pushed/popped onto the stack.
*
* (c) CPU_CRITICAL_METHOD_STATUS_LOCAL is one preferred method since it DOES support multiple
* levels of interrupts. However, this method assumes that the compiler provides C-level
* &/or assembly-level functionality for the following :
*
* ENTER CRITICAL SECTION :
* (a) Save interrupt status into a local variable
* (b) Disable interrupts
*
* EXIT CRITICAL SECTION :
* (c) Restore interrupt status from a local variable
*
* (2) Critical section macro's most likely require inline assembly. If the compiler does NOT
* allow inline assembly in C source files, critical section macro's MUST call an assembly
* subroutine defined in a 'cpu_a.asm' file located in the following software directory :
*
* \<CPU-Compiler Directory>\<cpu>\<compiler>\
*
* where
* <CPU-Compiler Directory> directory path for common CPU-compiler software
* <cpu> directory name for specific CPU
* <compiler> directory name for specific compiler
*
* (3) To save/restore interrupt status, a local variable 'cpu_sr' of type 'CPU_SR' MAY need to
* be declared (e.g. if 'CPU_CRITICAL_METHOD_STATUS_LOCAL' method is configured). Configure
* 'CPU_SR' data type with the appropriate-sized CPU data type large enough to completely
* store the CPU's/compiler's status word.
*********************************************************************************************************
*/
typedef CPU_INT32U CPU_SR; /* Defines CPU status register size (see Note #3). */
/* Configure CPU critical method (see Note #1) : */
#define CPU_CFG_CRITICAL_METHOD CPU_CRITICAL_METHOD_STATUS_LOCAL
#define CPU_CRITICAL_ENTER() { cpu_sr = CPU_SR_Save(); }
#define CPU_CRITICAL_EXIT() { CPU_SR_Restore(cpu_sr); }
/*
*********************************************************************************************************
* FUNCTION PROTOTYPES
*********************************************************************************************************
*/
void CPU_IntDis (void);
void CPU_IntEn (void);
void CPU_IntSrcDis (CPU_INT08U pos);
void CPU_IntSrcEn (CPU_INT08U pos);
CPU_INT16S CPU_IntSrcPrioGet(CPU_INT08U pos);
void CPU_IntSrcPrioSet(CPU_INT08U pos,
CPU_INT08U prio);
CPU_SR CPU_SR_Save (void);
void CPU_SR_Restore (CPU_SR cpu_sr);
CPU_INT32U CPU_CntLeadZeros (CPU_INT32U val);
CPU_INT32U CPU_RevBits (CPU_INT32U val);
void CPU_WaitForInt (void);
void CPU_WaitForExcept(void);
void CPU_BitBandClr (CPU_ADDR addr,
CPU_INT08U bit_nbr);
void CPU_BitBandSet (CPU_ADDR addr,
CPU_INT08U bit_nbr);
/*
*********************************************************************************************************
* INTERRUPT SOURCES
*********************************************************************************************************
*/
#define CPU_INT_STK_PTR 0
#define CPU_INT_RESET 1
#define CPU_INT_NMI 2
#define CPU_INT_HFAULT 3
#define CPU_INT_MEM 4
#define CPU_INT_BUSFAULT 5
#define CPU_INT_USAGEFAULT 6
#define CPU_INT_RSVD_07 7
#define CPU_INT_RSVD_08 8
#define CPU_INT_RSVD_09 9
#define CPU_INT_RSVD_10 10
#define CPU_INT_SVCALL 11
#define CPU_INT_DBGMON 12
#define CPU_INT_RSVD_13 13
#define CPU_INT_PENDSV 14
#define CPU_INT_SYSTICK 15
/*
*********************************************************************************************************
* CPU REGISTERS
*********************************************************************************************************
*/
#define CPU_REG_NVIC_NVIC (*((volatile CPU_INT32U *)(0xE000E004))) /* Int Ctrl'er Type Reg. */
#define CPU_REG_NVIC_ST_CTRL (*((volatile CPU_INT32U *)(0xE000E010))) /* SysTick Ctrl & Status Reg. */
#define CPU_REG_NVIC_ST_RELOAD (*((volatile CPU_INT32U *)(0xE000E014))) /* SysTick Reload Value Reg. */
#define CPU_REG_NVIC_ST_CURRENT (*((volatile CPU_INT32U *)(0xE000E018))) /* SysTick Current Value Reg. */
#define CPU_REG_NVIC_ST_CAL (*((volatile CPU_INT32U *)(0xE000E01C))) /* SysTick Calibration Value Reg. */
/* IRQ Set En Reg. */
#define CPU_REG_NVIC_SETEN(n) (*((volatile CPU_INT32U *)(0xE000E100 + (n) * 4)))
/* IRQ Clr En Reg. */
#define CPU_REG_NVIC_CLREN(n) (*((volatile CPU_INT32U *)(0xE000E180 + (n) * 4)))
/* IRQ Set Pending Reg. */
#define CPU_REG_NVIC_SETPEND(n) (*((volatile CPU_INT32U *)(0xE000E200 + (n) * 4)))
/* IRQ Clr Pending Reg. */
#define CPU_REG_NVIC_CLRPEND(n) (*((volatile CPU_INT32U *)(0xE000E280 + (n) * 4)))
/* IRQ Active Reg. */
#define CPU_REG_NVIC_ACTIVE(n) (*((volatile CPU_INT32U *)(0xE000E300 + (n) * 4)))
/* IRQ Prio Reg. */
#define CPU_REG_NVIC_PRIO(n) (*((volatile CPU_INT32U *)(0xE000E400 + (n) * 4)))
#define CPU_REG_NVIC_CPUID (*((volatile CPU_INT32U *)(0xE000ED00))) /* CPUID Base Reg. */
#define CPU_REG_NVIC_ICSR (*((volatile CPU_INT32U *)(0xE000ED04))) /* Int Ctrl State Reg. */
#define CPU_REG_NVIC_VTOR (*((volatile CPU_INT32U *)(0xE000ED08))) /* Vect Tbl Offset Reg. */
#define CPU_REG_NVIC_AIRCR (*((volatile CPU_INT32U *)(0xE000ED0C))) /* App Int/Reset Ctrl Reg. */
#define CPU_REG_NVIC_SCR (*((volatile CPU_INT32U *)(0xE000ED10))) /* System Ctrl Reg. */
#define CPU_REG_NVIC_CCR (*((volatile CPU_INT32U *)(0xE000ED14))) /* Cfg Ctrl Reg. */
#define CPU_REG_NVIC_SHPRI1 (*((volatile CPU_INT32U *)(0xE000ED18))) /* System Handlers 4 to 7 Prio. */
#define CPU_REG_NVIC_SHPRI2 (*((volatile CPU_INT32U *)(0xE000ED1C))) /* System Handlers 8 to 11 Prio. */
#define CPU_REG_NVIC_SHPRI3 (*((volatile CPU_INT32U *)(0xE000ED20))) /* System Handlers 12 to 15 Prio. */
#define CPU_REG_NVIC_SHCSR (*((volatile CPU_INT32U *)(0xE000ED24))) /* System Handler Ctrl & State Reg. */
#define CPU_REG_NVIC_CFSR (*((volatile CPU_INT32U *)(0xE000ED28))) /* Configurable Fault Status Reg. */
#define CPU_REG_NVIC_HFSR (*((volatile CPU_INT32U *)(0xE000ED2C))) /* Hard Fault Status Reg. */
#define CPU_REG_NVIC_DFSR (*((volatile CPU_INT32U *)(0xE000ED30))) /* Debug Fault Status Reg. */
#define CPU_REG_NVIC_MMFAR (*((volatile CPU_INT32U *)(0xE000ED34))) /* Mem Manage Addr Reg. */
#define CPU_REG_NVIC_BFAR (*((volatile CPU_INT32U *)(0xE000ED38))) /* Bus Fault Addr Reg. */
#define CPU_REG_NVIC_AFSR (*((volatile CPU_INT32U *)(0xE000ED3C))) /* Aux Fault Status Reg. */
#define CPU_REG_NVIC_PFR0 (*((volatile CPU_INT32U *)(0xE000ED40))) /* Processor Feature Reg 0. */
#define CPU_REG_NVIC_PFR1 (*((volatile CPU_INT32U *)(0xE000ED44))) /* Processor Feature Reg 1. */
#define CPU_REG_NVIC_DFR0 (*((volatile CPU_INT32U *)(0xE000ED48))) /* Debug Feature Reg 0. */
#define CPU_REG_NVIC_AFR0 (*((volatile CPU_INT32U *)(0xE000ED4C))) /* Aux Feature Reg 0. */
#define CPU_REG_NVIC_MMFR0 (*((volatile CPU_INT32U *)(0xE000ED50))) /* Memory Model Feature Reg 0. */
#define CPU_REG_NVIC_MMFR1 (*((volatile CPU_INT32U *)(0xE000ED54))) /* Memory Model Feature Reg 1. */
#define CPU_REG_NVIC_MMFR2 (*((volatile CPU_INT32U *)(0xE000ED58))) /* Memory Model Feature Reg 2. */
#define CPU_REG_NVIC_MMFR3 (*((volatile CPU_INT32U *)(0xE000ED5C))) /* Memory Model Feature Reg 3. */
#define CPU_REG_NVIC_ISAFR0 (*((volatile CPU_INT32U *)(0xE000ED60))) /* ISA Feature Reg 0. */
#define CPU_REG_NVIC_ISAFR1 (*((volatile CPU_INT32U *)(0xE000ED64))) /* ISA Feature Reg 1. */
#define CPU_REG_NVIC_ISAFR2 (*((volatile CPU_INT32U *)(0xE000ED68))) /* ISA Feature Reg 2. */
#define CPU_REG_NVIC_ISAFR3 (*((volatile CPU_INT32U *)(0xE000ED6C))) /* ISA Feature Reg 3. */
#define CPU_REG_NVIC_ISAFR4 (*((volatile CPU_INT32U *)(0xE000ED70))) /* ISA Feature Reg 4. */
#define CPU_REG_NVIC_SW_TRIG (*((volatile CPU_INT32U *)(0xE000EF00))) /* Software Trigger Int Reg. */
#define CPU_REG_MPU_TYPE (*((volatile CPU_INT32U *)(0xE000ED90))) /* MPU Type Reg. */
#define CPU_REG_MPU_CTRL (*((volatile CPU_INT32U *)(0xE000ED94))) /* MPU Ctrl Reg. */
#define CPU_REG_MPU_REG_NBR (*((volatile CPU_INT32U *)(0xE000ED98))) /* MPU Region Nbr Reg. */
#define CPU_REG_MPU_REG_BASE (*((volatile CPU_INT32U *)(0xE000ED9C))) /* MPU Region Base Addr Reg. */
#define CPU_REG_MPU_REG_ATTR (*((volatile CPU_INT32U *)(0xE000EDA0))) /* MPU Region Attrib & Size Reg. */
#define CPU_REG_DBG_CTRL (*((volatile CPU_INT32U *)(0xE000EDF0))) /* Debug Halting Ctrl & Status Reg. */
#define CPU_REG_DBG_SELECT (*((volatile CPU_INT32U *)(0xE000EDF4))) /* Debug Core Reg Selector Reg. */
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