aes_pkg.vhd

来自「wasdas zgfd xdfg dsg dsg v d d ccc」· VHDL 代码 · 共 63 行

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-- Company: IIT Guwahati
-- Student: Brijesh Singh
-- Guide: Dr. A.K. Mishra
-- Create Date:    19:41:54 04/15/2009 
-- Design Name: 
-- Module Name:    AES_pkg 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


package AES_pkg is

type ARRAY_256 is array (00 to 255) of std_logic_vector (07 downto 00);

type state is array (15 downto 00) of std_logic_vector (07 downto 00);

type state_column is array (03 downto 00) of std_logic_vector (07 downto 00);

type Key_block is array (00 to 175) of std_logic_vector (07 downto 00);

end AES_pkg;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


package xtime_pkg is

  function xtime ( x : std_logic_vector ) return std_logic_vector;

end xtime_pkg;

package body xtime_pkg is

  function xtime   ( x : std_logic_vector ) return std_logic_vector is
     variable xtime_variable  : std_logic_vector (07 downto 00) := ( X"00" );
     begin
        xtime_variable := (  x(6 downto 4)                     
                     & (x(3 downto 2) xor (x(7) & x(7)))  
                     &  x(1)                              
                     & (x(0) xor x(7))                    
                     &  x(7));                            
     return xtime_variable;
  end xtime;

end xtime_pkg;

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