test4.txt

vhdl数字设计实验,可以实现4x4小键盘的动态扫描

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity test is
  port(
        vh :buffer std_logic_vector(4 downto 1);
        clk :in std_logic;com :out std_logic;
        vv :in std_logic_vector(4 downto 1);
        output :out std_logic_vector(1 to 8));
end entity;

architecture test of test is
signal vh_vv :std_logic_vector(8 downto 1);
signal jishu :std_logic_vector(2 downto 1);
begin
process(clk)
begin
if(clk'event and clk='1')then
   com<='1';
   if jishu<3 then
   jishu<=jishu+1;
   else
   jishu<="00";
   end if;
 case jishu is
  when"00"=>vh<="1110";
  when"01"=>vh<="1101";
  when"10"=>vh<="1011";
  when"11"=>vh<="0111";
  when others=>null;
 end case;
 end if;
end process;
 vh_vv<=vh & vv;
with vh_vv select
    output<="00111111"when"11101110",
            "00000110"when"11101101",
            "01001111"when"11101011",
            "01100110"when"11100111",
            "01100110"when"11011110",
            "01101101"when"11011101",
            "01111101"when"11011011",
            "00000111"when"11010111",
            "01111111"when"10111110",
            "01101111"when"10111101",
            "01110111"when"10111011",
            "11111111"when"10110111",
            "00111001"when"01111110",
            "10111111"when"01111101",
            "01111001"when"01111011",
            "01110001"when"01110111",
            "00000000"when others;
 end architecture;