📄 qy2io.h
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/***********************************************************************
* HEADER_START *
* *
* Name: qt2io.h *
* Project: Sensorless BLDC Motor HC08 *
* Description: MC68HC08MR32 registers map include file *
* Processor: HC08MR32/24 *
* HW: *
* Revision: 0.1 *
* Date: 23rd July 2002 *
* Compiler: METROWERKS ANSI-C/cC++ Compiler for HC08 *
* V-5.0.12 ICG *
* Author: Libor Prokop, Radim Visinka *
* Company: Motorola SPS *
* Roznov System Application Laboratory *
* Roznov pod Radhostem, Czech Republic *
* Security: General Business Information *
* *
* =================================================================== *
* Copyright (c): MOTOROLA Inc.,2002, All rights reserved. *
* *
* =================================================================== *
* THIS SOFTWARE IS PROVIDED BY MOTOROLA RSAL "AS IS" AND ANY *
* EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR *
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MOTOROLA RSAL OR *
* ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT *
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; *
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) *
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, *
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED *
* OF THE POSSIBILITY OF SUCH DAMAGE. *
* =================================================================== *
*
* HEADER_END
*/
#ifndef _QY2IO_H
#define _QY2IO_H
/******************************************************************************/
/* I N C L U D E H E A D E R F I L E S */
/******************************************************************************/
#include "qy2_bit.h" /* file contains MR32 flags definition */
/******************************************************************************/
/* REGISTERS DEFINITIONS */
/******************************************************************************/
/* PORTS section
*/
#define PORTA (*(volatile PORTA_Def*)(0x00)) /* port A */
#define PORTB (*(volatile PORTB_Def*)(0x01)) /* port B */
#define DDRA (*(volatile char*)(0x04)) /* data direction port A */
#define DDRB (*(volatile char*)(0x05)) /* data direction port B */
/* Input Pullup Enable section
*/
#define PTAPUE (*(volatile PTAPUE_Def*)(0x0B)) /*PTAPUE*/
#define PTBPUE (*(volatile PTBPUE_Def*)(0x0C)) /*PTAPUE*/
/* IRQ Status and Control
*/
#define INTSCR (*(volatile INTSCR_Def*)(0x1D)) /*IRQ Status and Control*/
/* OPTION section
*/
#define CONFIG2 (*(volatile CONFIG2_Def*)(0x1E)) /* CONFIG Configuration Write-Once Register */
#define CONFIG1 (*(volatile CONFIG1_Def*)(0x1F)) /* CONFIG Configuration Write-Once Register */
/* A TIMER section
*/
#define TSC (*(volatile TSC_Def*)(0x20)) /* timer status/ctrl register */
#define TCNT (*(volatile int*)(0x21)) /* TIM Counter Register*/
#define TCNTH (*(volatile char*)(0x21)) /* TIM Counter Register High */
#define TCNTL (*(volatile char*)(0x22)) /*TIM Counter Register Low*/
#define TMOD (*(volatile int*)(0x23)) /* timer modulo register */
#define TMODH (*(volatile char*)(0x23)) /* timer modulo high */
#define TMODL (*(volatile char*)(0x24)) /* timer modulo low */
#define TSC0 (*(volatile TSC0_Def*)(0x25)) /* timer channel 0 status/ctrl */
#define TCH0 (*(volatile int*)(0x26)) /* timer channel 0 register */
#define TCH0H (*(volatile char*)(0x26)) /* timer channel 0 high */
#define TCH0L (*(volatile char*)(0x27)) /* timer channel 0 low */
#define TSC1 (*(volatile TSC1_Def*)(0x28)) /* timer channel 1 status/ctrl */
#define TCH1 (*(volatile int*)(0x29)) /* timer channel 1 register */
#define TCH1H (*(volatile char*)(0x29)) /* timer channel 1 high */
#define TCH1L (*(volatile char*)(0x2a)) /* timer channel 1 low */
/* OSCTRIM section */
/* OSC section */
#define OSCSTAT (*(volatile char*)(0x36)) /* OSCSTAT register */
#define OSCTRIM (*(volatile char*)(0x38)) /* OSCTRIM register */
#define TRIMLOC (*(volatile char*)(0xFFC0)) /* OSCTRIMLOC */
/* INTERRUPT section
*/
#define ISCR (*(volatile char*)(0x3F)) /* IRQ status/control register */
/* A/D section
*/
#define ADSCR (*(volatile ADSCR_Def*)(0x3c)) /* ADC status and control register */
#define ADR (*(volatile char*)(0x3E)) /* ADC data register */
#define ADICLK (*(volatile ADICLK_Def*)(0x3F)) /* ADC clock register */
/****************** Flash Program Address ******************************/
#define CTRLBYT (*(volatile unsigned char*) (0x88)) //存放控制位的RAM地址
#define CPUSPD (*(volatile unsigned char*) (0x89)) //存总线速度的RAM地址
//LADDRH,LADDRL存储FLASH编程末尾地址的RAM地址
#define LADDRH (*(volatile unsigned char*) (0x8A))
#define LADDRL (*(volatile unsigned char*) (0x8B))
#define FLASH_TEST_ADDRESS 0xFD40 //存放数据的FLASH页的首地址
/****************************** End *************************************/
#endif /* _QT2IO_H */
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