adsuart.tan.summary

基于FPGA的信号采集及频谱分析

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.871 ns
From           : d[0]
To             : sld_signaltap:UART|acq_trigger_in_reg[1]
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 15.117 ns
From           : suart:iUART|u_xmit:iXMIT|state~22
To             : txd
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 4.895 ns
From           : clk1
To             : AD_CLK
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.487 ns
From           : altera_internal_jtag
To             : sld_signaltap:UART|bypass_reg_out
From Clock     : 
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.695 ns
From           : suart:iUART|u_xmit:iXMIT|partoser[0]
To             : txd
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 75.19 MHz ( period = 13.299 ns )
From           : adsram:iadc|LPMRAM:u1|altsyncram:altsyncram_component|altsyncram_ut01:auto_generated|altsyncram_hkb2:altsyncram1|ram_block3a2~porta_address_reg9
To             : xdata[0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 80.33 MHz ( period = 12.448 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]
To             : sld_hub:sld_hub_inst|HUB_TDO~reg0
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'clk1'
Slack          : N/A
Required Time  : None
Actual Time    : 140.08 MHz ( period = 7.139 ns )
From           : adsram:iadc|lpm_counter:addr_rtl_7|cntr_rb7:auto_generated|safe_q[3]
To             : adsram:iadc|address[3]
From Clock     : clk1
To Clock       : clk1
Failed Paths   : 0

Type           : Clock Hold: 'clk1'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : adsram:iadc|address[2]
To             : adsram:iadc|LPMRAM:u1|altsyncram:altsyncram_component|altsyncram_ut01:auto_generated|altsyncram_hkb2:altsyncram1|ram_block3a2~porta_address_reg2
From Clock     : clk1
To Clock       : clk1
Failed Paths   : 30

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : suart:iUART|u_xmit:iXMIT|xmit_cmd_p
To             : suart:iUART|u_xmit:iXMIT|xmit_done
From Clock     : clk
To Clock       : clk
Failed Paths   : 21

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 51

--------------------------------------------------------------------------------------