u_baud.vhd

来自「基于FPGA的信号采集及频谱分析」· VHDL 代码 · 共 51 行

-- SUART Project
-- 
-- BAUD.vhd 
-- 波特率发生器（SUART模块）
--
-- Design By jy2010
-- Update:
-- 		19/12/2002 归档

library	ieee;
use	ieee.std_logic_1164.all;
use	ieee.std_logic_arith.all;
use	ieee.std_logic_unsigned.all;

ENTITY u_baud IS
	GENERIC(XTAL_CLK : integer :=  12000000;
			BAUD : integer := 9600;
			CLK_DIV_coef :	integer	:= 39;--XTAL_CLK / (BAUD * 16 * 2);
			-- CW >= log2(CLK_DIV)
	        cw : integer:=  11);
	PORT(
		clk		: IN	STD_LOGIC;
		resetL	: IN	STD_LOGIC;
		bclk	: OUT	STD_LOGIC);
END u_baud;

ARCHITECTURE behv OF u_baud IS	

	SIGNAL clk_div	: STD_LOGIC_VECTOR(cw-1 downto 0);
	signal bclk_t	:	std_logic;
BEGIN

process(clk,resetL)
begin
	if(resetL = '0') then
		clk_div <= (others => '0');
		bclk_t <= '0';
	elsif(clk'event and clk = '1') then
		if(clk_div = clk_div_coef) then
			clk_div <= (others => '0');
			bclk_t <= not bclk_t;
		else
			clk_div <= clk_div + 1;
		end if;
	end if;
end	process;

bclk <= bclk_t;

end	behv;