dds_vhdl.fit.summary

来自「基于FPGA的移相式DDS正弦信号发生器的VHDL源代码」· SUMMARY 代码 · 共 12 行

Flow Status : Successful - Mon Aug 01 11:16:00 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : dds_vhdl
Top-level Entity Name : DDS_VHDL
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Production
Total logic elements : 738 / 2,910 ( 25 % )
Total pins : 38 / 104 ( 36 % )
Total memory bits : 39,424 / 59,904 ( 65 % )
Total PLLs : 0 / 1 ( 0 % )