dds_vhdl.map.summary

基于FPGA的移相式DDS正弦信号发生器的VHDL源代码

Flow Status : Successful - Mon Aug 01 11:15:26 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : dds_vhdl
Top-level Entity Name : DDS_VHDL
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Production
Total logic elements : 815
Total pins : 42
Total memory bits : 39,424
Total PLLs : 0