dds_vhdl.vhd

基于FPGA的移相式DDS正弦信号发生器的VHDL源代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS_VHDL IS                                     -- 顶层设计
    PORT (      CLK : IN  STD_LOGIC;
             CLK_DA : OUT  STD_LOGIC;
              FWORD : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
              PWORD : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
              FOUT  : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
              POUT  : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)   );
 END;
ARCHITECTURE one OF DDS_VHDL IS
    COMPONENT REG32B
        PORT (  LOAD : IN STD_LOGIC;
                 DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );
    END COMPONENT;
     COMPONENT REG10B
        PORT (  LOAD :  IN STD_LOGIC;
                 DIN :  IN STD_LOGIC_VECTOR(9 DOWNTO 0);
                DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) );
    END COMPONENT;
    COMPONENT ADDER32B
       PORT (  A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
               B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
               S : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)     );
    END COMPONENT;
    COMPONENT ADDER10B
       PORT (  A : IN  STD_LOGIC_VECTOR(9 DOWNTO 0);
               B : IN  STD_LOGIC_VECTOR(9 DOWNTO 0);
               S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)     );
    END COMPONENT;
    COMPONENT SIN_ROM
      PORT	( address	: IN STD_LOGIC_VECTOR(9 DOWNTO 0);
		      inclock	: IN STD_LOGIC ;
	            	q	: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)	);
    END COMPONENT; 
     SIGNAL F32B   : STD_LOGIC_VECTOR(31 DOWNTO 0);
     SIGNAL D32B   : STD_LOGIC_VECTOR(31 DOWNTO 0);
     SIGNAL DIN32B : STD_LOGIC_VECTOR(31 DOWNTO 0);
     SIGNAL P10B   : STD_LOGIC_VECTOR( 9 DOWNTO 0);
     SIGNAL LIN10B : STD_LOGIC_VECTOR( 9 DOWNTO 0);
     SIGNAL SIN10B : STD_LOGIC_VECTOR( 9 DOWNTO 0);
     SIGNAL DOUT   : STD_LOGIC_VECTOR (9 DOWNTO 0);
     SIGNAL FFOUT  : STD_LOGIC_VECTOR (9 DOWNTO 0);
     SIGNAL DIN:   STD_LOGIC_VECTOR(7 DOWNTO 0); 

 BEGIN 
 F32B(27 DOWNTO 20)<=FWORD ;
 F32B(31 DOWNTO 28)<="0000";
 F32B(19 DOWNTO 0)<="00000000000000000000" ;
 P10B( 9 DOWNTO 2)<=PWORD ;
 P10B( 1 DOWNTO 0)<="00"  ;
           CLK_DA <= NOT CLK;
 
 u1 : ADDER32B  PORT MAP( A=>F32B,B=>D32B, S=>DIN32B );
 u2 :   REG32B  PORT MAP( DOUT=>D32B,DIN=> DIN32B, LOAD=>CLK );
 u3 :  SIN_ROM  PORT MAP( address=>SIN10B, q=>FOUT, inclock=>CLK );
 u4 : ADDER10B  PORT MAP( A=>P10B,B=>D32B(31 DOWNTO 22),S=>LIN10B );
 u5 :   REG10B  PORT MAP( DOUT=>SIN10B,DIN=>LIN10B, LOAD=>CLK );
 u6 :  SIN_ROM  PORT MAP( address=>D32B(31 DOWNTO 22), q=>POUT, inclock=>CLK );
 

END;