📄 fullbridgeinverter.mdl
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Value "1"
VectorParams1D on
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
SampleTime "inf"
}
Block {
BlockType DataTypeConversion
OutDataTypeMode "Inherit via back propagation"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
ConvertRealWorld "Real World Value (RWV)"
RndMeth "Zero"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Demux
Outputs "4"
DisplayOption "none"
BusSelectionMode off
}
Block {
BlockType EnablePort
StatesWhenEnabling "held"
ShowOutputPort off
ZeroCross on
}
Block {
BlockType From
IconDisplay "Tag"
}
Block {
BlockType Gain
Gain "1"
Multiplication "Element-wise(K.*u)"
ParameterDataTypeMode "Same as input"
ParameterDataType "sfix(16)"
ParameterScalingMode "Best Precision: Matrix-wise"
ParameterScaling "2^0"
OutDataTypeMode "Same as input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Goto
IconDisplay "Tag"
}
Block {
BlockType Ground
}
Block {
BlockType Inport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchByCopyingInsideSignal off
Interpolate on
}
Block {
BlockType Logic
Operator "AND"
Inputs "2"
AllPortsSameDT on
OutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
SampleTime "-1"
}
Block {
BlockType Mux
Inputs "4"
DisplayOption "none"
UseBusObject off
BusObject "BusObject"
NonVirtualBus off
}
Block {
BlockType Outport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType PMComponent
SubClassName "unknown"
}
Block {
BlockType PMIOPort
}
Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Zero"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Reference
}
Block {
BlockType RelationalOperator
Operator ">="
InputSameDT on
LogicOutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Saturate
UpperLimit "0.5"
LowerLimit "-0.5"
LinearizeAsGain on
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Scope
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "-1"
}
Block {
BlockType Selector
InputType "Vector"
IndexMode "One-based"
ElementSrc "Internal"
Elements "1"
RowSrc "Internal"
Rows "1"
ColumnSrc "Internal"
Columns "1"
InputPortWidth "-1"
IndexIsStartValue off
OutputPortSize "1"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
Block {
BlockType SignalGenerator
WaveForm "sine"
TimeSource "Use simulation time"
Amplitude "1"
Frequency "1"
Units "Hertz"
VectorParams1D on
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Switch
Criteria "u2 >= Threshold"
Threshold "0"
InputSameDT on
OutDataTypeMode "Inherit via internal rule"
RndMeth "Floor"
SaturateOnIntegerOverflow on
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Terminator
}
Block {
BlockType ToWorkspace
VariableName "simulink_output"
MaxDataPoints "1000"
Decimation "1"
SampleTime "0"
FixptAsFi off
}
Block {
BlockType TransferFcn
Numerator "[1]"
Denominator "[1 2 1]"
AbsoluteTolerance "auto"
Realization "auto"
}
Block {
BlockType Trigonometry
Operator "sin"
OutputSignalType "auto"
SampleTime "-1"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "FullbridgeInverter"
Location [2, 82, 997, 704]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "C"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [691, 385, 709, 420]
Orientation "down"
NamePlacement "alternate"
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "C"
Resistance "1"
Inductance "1e-3"
SetiL0 off
InitialCurrent "0"
Capacitance "6.3e-6"
Setx0 off
InitialVoltage "0"
Measurements "Branch voltage and current"
}
Block {
BlockType Demux
Name "Demux"
Ports [1, 4]
Position [590, 546, 595, 584]
BackgroundColor "black"
ShowName off
DisplayOption "bar"
}
Block {
BlockType Demux
Name "Demux1"
Ports [1, 4]
Position [230, 147, 235, 223]
Orientation "left"
BackgroundColor "black"
ShowName off
DisplayOption "bar"
}
Block {
BlockType SubSystem
Name "Double click here for info"
Ports []
Position [1010, 640, 1040, 668]
DropShadow on
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskHideContents off
MaskDisplay "disp('?')"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
System {
Name "Double click here for info"
Location [75, 151, 967, 845]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
Annotation {
Name "G. Sybille (Hydro-Quebec)"
Position [32, 67]
HorizontalAlignment "left"
VerticalAlignment "top"
UseDisplayTextAsClickCallback off
FontName "Arial"
FontSize 12
}
Annotation {
Name "Demonstration"
Position [34, 337]
HorizontalAlignment "left"
ForegroundColor "blue"
UseDisplayTextAsClickCallback off
FontSize 14
FontWeight "bold"
}
Annotation {
Name "Circuit Description"
Position [29, 102]
HorizontalAlignment "left"
ForegroundColor "blue"
UseDisplayTextAsClickCallback off
FontSize 14
FontWeight "bold"
}
Annotation {
Name "This demonstration illustrates use of the I"
"GBT/Diode block in voltage-sourced converters\nIt also demonstrates harmonic "
"analysis of PWM waveforms using the Powergui/FFT tool. "
Position [29, 22]
HorizontalAlignment "left"
VerticalAlignment "top"
UseDisplayTextAsClickCallback off
FontSize 14
FontWeight "bold"
}
Annotation {
Name "The system consists of two independant circ"
"uits illustrating single-phase PWM voltage-sourced converters (VSC).\n\n1. Ha"
"lf-bridge converter \n2. Full-bridge converter \n\nThe converters are built "
"with the IGBT/Diode block which is the basic building block of all VSCs. The "
"IGBT/Diode block is a simplified model \nof an IGBT (or GTO or MOSFET)/Diode "
"pair where the forward voltages of the forced-commutated device and diode are"
" ignored. \nYou may replace these blocks by individual IGBT and diode blocks "
"for a more detailed representation.\nVSCs are controlled in open loop with th"
"e Discrete PWM Generator block available in the Extras/Discrete Control Block"
"s library.\nThe two circuits use the same DC voltage (Vdc = 400V), carrier fr"
"equency (1080 Hz) and modulation index (m = 0.8) .\n\nIn order to allow furth"
"er signal processing, signals displayed on the two Scope blocks (sampled at "
"simulation sampling rate of 3240 samples/cycle)\nare stored in two variables"
" named 'sps1phPWM1_str' and 'sps1phPWM2_str' (structures with time)."
Position [31, 115]
HorizontalAlignment "left"
VerticalAlignment "top"
UseDisplayTextAsClickCallback off
FontName "Arial"
FontSize 12
}
Annotation {
Name "Run the simulation and observe the followin"
"g two waveforms on the two Scope blocks:\nCurrent into the load (trace 1), Vo"
"ltage generated by the PWM inverter (trace 2). \n\nOnce the simulation is co"
"mpleted, open the Powergui and select \"FFT Analysis\" to display the 0 - 500"
"0 Hz frequency spectrum of signals saved \nin the three \"sps1phPWMx_str\" st"
"ructures. The FFT will be performed on a 2-cycle window starting at t = 0.1 "
"- 2/60 (last 2 cycles of recording). \nFor each circuit, selelect Input label"
"ed \"V inverter\" . Click on \"Display\" and observe the frequency spectrum o"
"f last 2 cycles.\n\nThe fundamental component of V inverter is displayed ab"
"ove the spectrum window.\nCompare the magnitude of the fundamental component "
"of the inverter voltage with the theoretical values given in the circuit.\nC"
"ompare also the harmonic contents in the inverter voltage.\n\nThe half-bridge"
" inverter generates a bipolar voltage (-200V or +200V) .\nHarmonics occur aro"
"und the carrier frequency (1080 Hz +- k*60 Hz), with a maximum of 103% at 108"
"0 Hz.\n\nThe full-bridge inverter generates a monopolar voltage varying betwe"
"en 0 and+400V for one half cycle and then between 0 and -400V for the next ha"
"lf cycle.\nFor the same DC voltage and modulation index, the fundamental comp"
"onent magnitude is twice the value obtained with the half-bridge. \nHarmonics"
" generated by the full-bridge are lower and they appear at double of the carr"
"ier frequency (maximum of 40% at 2*1080+-60 Hz)\n As a result, the current ob"
"tained with the full-bridge is smoother.\n\nIf you now perform a FFT on the s"
"ignal \"I load\" you will notice that the THD of load current is 7.3% for the"
" half-bridge inverter as compared to\nonly 2% for the full-bridge inverter."
Position [31, 360]
HorizontalAlignment "left"
VerticalAlignment "top"
UseDisplayTextAsClickCallback off
FontName "Arial"
FontSize 12
}
}
}
Block {
BlockType From
Name "From2"
Position [220, 296, 260, 314]
ShowName off
CloseFcn "tagdialog Close"
GotoTag "G1_2"
}
Block {
BlockType From
Name "From3"
Position [215, 426, 255, 444]
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