📄 cpu.s
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__DEC_L: _DEC L _end__DEC_$HL: movl HL, %eax _readb movb %al, %dl _DEC %dl movl HL, %eax _writeb _end__DEC_A: _DEC %bh _end __INC_BC: _INCW BC__INC_DE: _INCW DE__INC_HL: _INCW HL__INC_SP: _INCW SP__DEC_BC: _DECW BC__DEC_DE: _DECW DE__DEC_HL: _DECW HL__DEC_SP: _DECW SP __ADD_SP_IMM: _fetchs _ADDSP _end__RLCA: _RLCA _end__RRCA: _RRCA _end__RLA: _RLA _end__RRA: _RRA _end__DAA: _DAA _end__SCF: andb $0x8f, %bl orb $0x10, %bl _end__CCF: andb $0x9f, %bl xorb $0x10, %bl _end__CPL: orb $0x60, %bl xorb $-1, %bh _end __EI: movl $1, IMA _end__DI: movl $0, IME movl $0, IMA _end__PUSH_BC: movl BC, %eax jmp __PUSH__PUSH_DE: movl DE, %eax jmp __PUSH__PUSH_HL: movl HL, %eax jmp __PUSH__PUSH_AF: movl %ebx, %eax__PUSH: _push _end__POP_BC: _pop movl %eax, BC _end__POP_DE: _pop movl %eax, DE _end__POP_HL: _pop movl %eax, HL _end__POP_AF: _pop movl %eax, %ebx _end __JR_NZ: testb $0x80, %bl jz __JR _NOJR _end__JR_Z: testb $0x80, %bl jnz __JR _NOJR _end__JR_NC: testb $0x10, %bl jz __JR _NOJR _end__JR_C: testb $0x10, %bl jnz __JR _NOJR _end__JR: _JR _end __JP_HL: movl HL, %eax movl %eax, %ebp _end__JP_NZ: testb $0x80, %bl jz __JP _NOJP _end__JP_Z: testb $0x80, %bl jnz __JP _NOJP _end__JP_NC: testb $0x10, %bl jz __JP _NOJP _end__JP_C: testb $0x10, %bl jnz __JP _NOJP _end__JP: _JP _end__CALL_NZ: testb $0x80, %bl jz __CALL _NOCALL _end__CALL_Z: testb $0x80, %bl jnz __CALL _NOCALL _end__CALL_NC: testb $0x10, %bl jz __CALL _NOCALL _end__CALL_C: testb $0x10, %bl jnz __CALL _NOCALL _end __CALL: _CALL _end __RET_NZ: testb $0x80, %bl jz __RET _NORET _end__RET_Z: testb $0x80, %bl jnz __RET _NORET _end__RET_NC: testb $0x10, %bl jz __RET _NORET _end__RET_C: testb $0x10, %bl jnz __RET _NORET _end__RETI: movl $1, %eax movl %eax, IME movl %eax, IMA__RET: _RET _end __RST_00: movl $0x00, %eax jmp __RST__RST_08: movl $0x08, %eax jmp __RST__RST_10: movl $0x10, %eax jmp __RST__RST_18: movl $0x18, %eax jmp __RST__RST_20: movl $0x20, %eax jmp __RST__RST_28: movl $0x28, %eax jmp __RST__RST_30: movl $0x30, %eax jmp __RST__RST_38: movl $0x38, %eax__RST: pushl %eax movl %ebp, %eax _push popl %ebp _end __HALT: movl $1, %eax movl %eax, halt _end__STOP: movb KEY1, %al testb $1, %al jz .Loldstop movb speed, %ah xorb $1, %ah movb %ah, speed shlb $7, %ah andb $0x7e, %al orb %ah, %al movb %al, KEY1.Loldstop: incw %bp _end __CB_OPS: _fetch xorl %ecx, %ecx movb cb_cycles_table(%eax), %cl movl %ecx, %edi jmp *cb_optable(,%eax,4) _make_cb_ops B _make_cb_ops C _make_cb_ops D _make_cb_ops E _make_cb_ops H _make_cb_ops L__RLC_A: _RLC %bh _end__RRC_A: _RRC %bh _end__RL_A: _RL %bh _end__RR_A: _RR %bh _end__SLA_A: _SLA %bh _end__SRA_A: _SRA %bh _end__SWAP_A: _SWAP_A__SRL_A: _SRL %bh _end__BIT_0_A: _BIT 0, %bh__BIT_1_A: _BIT 1, %bh__BIT_2_A: _BIT 2, %bh__BIT_3_A: _BIT 3, %bh__BIT_4_A: _BIT 4, %bh__BIT_5_A: _BIT 5, %bh__BIT_6_A: _BIT 6, %bh__BIT_7_A: _BIT 7, %bh__RES_0_A: _RES 0, %bh__RES_1_A: _RES 1, %bh__RES_2_A: _RES 2, %bh__RES_3_A: _RES 3, %bh__RES_4_A: _RES 4, %bh__RES_5_A: _RES 5, %bh__RES_6_A: _RES 6, %bh__RES_7_A: _RES 7, %bh__SET_0_A: _SET 0, %bh__SET_1_A: _SET 1, %bh__SET_2_A: _SET 2, %bh__SET_3_A: _SET 3, %bh__SET_4_A: _SET 4, %bh__SET_5_A: _SET 5, %bh__SET_6_A: _SET 6, %bh__SET_7_A: _SET 7, %bh _make_cb_hl_op RLC _make_cb_hl_op RRC _make_cb_hl_op RL _make_cb_hl_op RR _make_cb_hl_op SLA _make_cb_hl_op SRA__SWAP_$HL: _SWAP_MEM _make_cb_hl_op SRL _make_cb_hl_bit_op BIT, 0 _make_cb_hl_bit_op BIT, 1 _make_cb_hl_bit_op BIT, 2 _make_cb_hl_bit_op BIT, 3 _make_cb_hl_bit_op BIT, 4 _make_cb_hl_bit_op BIT, 5 _make_cb_hl_bit_op BIT, 6 _make_cb_hl_bit_op BIT, 7 _make_cb_hl_bit_op RES, 0 _make_cb_hl_bit_op RES, 1 _make_cb_hl_bit_op RES, 2 _make_cb_hl_bit_op RES, 3 _make_cb_hl_bit_op RES, 4 _make_cb_hl_bit_op RES, 5 _make_cb_hl_bit_op RES, 6 _make_cb_hl_bit_op RES, 7 _make_cb_hl_bit_op SET, 0 _make_cb_hl_bit_op SET, 1 _make_cb_hl_bit_op SET, 2 _make_cb_hl_bit_op SET, 3 _make_cb_hl_bit_op SET, 4 _make_cb_hl_bit_op SET, 5 _make_cb_hl_bit_op SET, 6 _make_cb_hl_bit_op SET, 7 .text .p2align 5cpu_emulate: pushl %ebp pushl %ebx pushl %esi pushl %edi movl AF, %ebx movl PC, %ebp movl 20(%esp), %esi cmpl $0, %esi jle .Ldone.Lnext: movl halt, %eax andl IME, %eax jnz .Lidle.Ldoop: # check for pending interrupts movl IME, %eax testl %eax, %eax jz .Lnoint movb IF, %cl movb IE, %al andb %cl, %al jnz .Lint.Lnoint: # update interrupt master enable movl IMA, %eax movl %eax, IME.Lendint: _trace _fetch xorl %ecx, %ecx movb cycles_table(%eax), %cl movl %ecx, %edi jmp *optable(,%eax,4) __NOP:__LD_B_B:__LD_C_C:__LD_D_D:__LD_E_E:__LD_H_H:__LD_L_L:__LD_A_A:opdone: shll $1, %edi # advance div movl %edi, %ecx movb div, %al addl %ecx, %ecx movb DIV, %ah addl %ecx, %eax movb %al, div movb %ah, DIV # advance timer movb TAC, %cl testb $0x04, %cl jnz .Ltimer.Lendtimer: movb speed, %cl shrl %cl, %edi # advance lcdc subl %edi, lcdc jg .Lnolcdc call lcdc_trans.Lnolcdc: # increment sound cycle counter addl %edi, snd # count off cycles used subl %edi, %esi jg .Lnext jmp .Ldone.Lint: # throw an interrupt xorl %edx, %edx movb int_mask_table(%eax), %ch movl %edx, IMA andb %ch, %cl movl %edx, IME movb %cl, IF movl int_vec_table(,%eax,4), %edx movl %ebp, %eax movl %edx, %ebp _push jmp .Lendint.Ltimer: xorb $0xff, %cl movl %edi, %eax incb %cl movl tim, %edx andb $0x03, %cl addb %cl, %cl shll %cl, %eax addl %eax, %edx movl %edx, tim cmpl $512, %edx jl .Lendtimer xorl %eax, %eax movl %edx, %ecx movb TIMA, %al shrl $9, %ecx andl $0x1ff, %edx addl %ecx, %eax movl %edx, tim movb %al, TIMA cmpl $256, %eax jl .Lendtimer movb $4, %cl xorl %edx, %edx orb %cl, IF movl $256, %ecx movb TMA, %dl subl $256, %eax subl %edx, %ecx.Ltimermod: subl %ecx, %eax jnc .Ltimermod movb %al, TIMA jmp .Lendtimer.Ldone: movl %ebx, AF movl %ebp, PC movl 20(%esp), %eax subl %esi, %eax popl %edi popl %esi popl %ebx popl %ebp ret.Lidle: pushl %esi call cpu_idle popl %ecx testl %eax, %eax jz .Ldoop subl %eax, %esi jg .Lnext jmp .Ldonecpu_step: movl 20(%esp), %edx movl halt, %eax andl IME, %eax jz .Lruncpu pushl %edx pushl %edx call cpu_idle popl %edx popl %edx subl %eax, %edx jnz .Lruncpu ret.Lruncpu: pushl $1 call cpu_emulate popl %edx ret⌨️ 快捷键说明
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