par2ser.txt

来自「并/串转换器即并行输入、串行输出转换器」· 文本 代码 · 共 114 行

并/串转换器即并行输入、串行输出转换器，例如一个8bit输入的并/串转换器，输出时钟频率是输入时钟频率的8倍，输入端一个时钟到来，8个输入端口同时输入数据；输出端以8倍的速度将并行输入的8bit串行输出，至于从高位输出还是从低位输出，可以再程序中指定。
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity ptos is
  port(
       rst:in std_logic;
       clk:in std_logic;
       start:in std_logic;
       data_in:in std_logic_vector(7 downto 0);
       data_valid:out std_logic;
       ready:out std_logic;
       q:out std_logic);
  end ptos;

architecture example of ptos is 
signal reg:std_logic_vector(7 downto 0);
signal cnt:std_logic_vector(3 downto 0);
signal reg_en:std_logic;
signal shift_start:std_logic;
type state is(idle,recieve,shift,finish);
signal current_state,next_state:state;

begin
counter:process(rst,clk,shift_start)
begin
     if(rst='0')then
       cnt<=(others=>'0');
     elsif(clk'event and clk='1')then 
        if(shift_start='0')then
           cnt<=cnt+1;
        else 
           cnt<=(others=>'0');
        end if;
     end if;
end process counter;

fsm:block
    begin
         sync:process(rst,clk)
         begin
              if(rst='0')then
                 current_state<=idle;
              elsif(clk'event and clk='1')then
                 current_state<=next_state;
              end if;
    end process sync;

    comb:process(current_state,cnt,start)
    begin
         case current_state is
              when idle=>
                   ready<='0';
                   reg_en<='1';
                   shift_state<='1';
                   data_valid<='1';
                   if(start='0')then
                        reg_en<='0';
                        next_state<=recieve;
                   else
                        next_state<=idle;
                   end if;
              when receieve=>
                   reg_en<='1';
                   ready<='1';
                   data_valid<='0';
                   shift_start<='0';
                   next_state<=shift;
              when shift=>
                   reg_en<='1';
                   ready<='1';
                   data_valid<='0';
                   if(cnt=8)then
                      shift_start<='1';
                      next_state<=finish;
                   else
                      shift_start<='0';
                      next_state<=shift;
                   end if;
              when finish=>
                   reg_en<='1';
                   ready<='0';
                   data_valid<='1';
                   shift_start<='1';
                   next_state<=idle;
              when others=>
                   next_state<=idle;
         end case;
    end process comb;
end block fsm;

data_channel:process(rst,clk)
    begin
      if(rst='0')then
           reg<=(others=>'0');
           q<='0';
      elsif(clk'event and clk='1')then
           if(reg_en='0')then
              reg<=data_in;
           elsif(shift_start='0')then
              q<=reg(7);
              for I in 7 downto 1  loop
                 reg(I)<=reg(I-1);
              end loop;
              reg(0)<='0';
           else
              q<='0';
           end if;
      end if;
end process data_channel;

end example;