pc.v

cup 的设计源代码

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    15:27:11 10/08/08
// Design Name:    
// Module Name:    PC
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module PC(clk, rst, PC_in, load_enable, count_enable, PC_out);
	parameter width=8;

    input clk;
    input rst;
    input[width-1:0] PC_in;
    input load_enable;
    input count_enable;
    output[width-1:0] PC_out;

	 reg[width-1:0] PC_out;

	 always@(posedge clk or negedge rst)
	 begin 
		 if(~rst)
		 	PC_out<='b0;
		 else if(load_enable)
		 	PC_out<=PC_in;
		 else if(count_enable)
		 	PC_out<=PC_out+1;
		 else 
		 	PC_out<=PC_out;
	 end

endmodule