register.v

cup 的设计源代码

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    15:48:20 10/08/08
// Design Name:    
// Module Name:    reg
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module register(clk, rst, load_enable, reg_in, reg_out);
	 parameter width=8;

    input clk;
    input rst;
    input load_enable;
    input[width-1:0] reg_in;
    output[width-1:0] reg_out;

	 reg[width-1:0] reg_out;

	 always@(posedge clk or negedge rst)
	 begin
		 if(~rst)
		 	reg_out<='b0;
		 else if(load_enable)
		 	reg_out<=reg_in;
		 else
		 	reg_out<=reg_out;
	 end

endmodule