__projnav.log

cup 的设计源代码

   Number of GCLKs                     3 out of 4      75%
   Number of External GCLKIOBs         1 out of 4      25%
      Number of LOCed GCLKIOBs         1 out of 1     100%

   Number of External IOBs            20 out of 166    12%
      Number of LOCed IOBs            20 out of 20    100%

   Number of SLICEs                  465 out of 1200   38%


Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98a3df) REAL time: 0 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.23
Phase 3.23 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 0 secs 

Phase 6.8
...............
Phase 6.8 (Checksum:a51edb) REAL time: 1 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 1 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 1 secs 

Writing design to file CPU.ncd


Total REAL time to Placer completion: 1 secs 
Total CPU time to Placer completion: 0 secs 

Starting Router

Phase 1: 3381 unrouted;       REAL time: 1 secs 

Phase 2: 3278 unrouted;       REAL time: 1 secs 

Phase 3: 1095 unrouted;       REAL time: 1 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|               DIVLE |      GCLKBUF1| No   |   21 |  0.077     |  0.493      |
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      GCLKBUF3| No   |   73 |  0.073     |  0.523      |
+---------------------+--------------+------+------+------------+-------------+
|               MULLE |      GCLKBUF0| No   |   17 |  0.046     |  0.492      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  71 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file CPU.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file 'v100.nph' in environment
C:/Xilinx.
   "CPU" is an NCD, version 3.1, device xcv100, package pq240, speed -4

Analysis completed Fri Nov 21 11:14:34 2008
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 1 secs 







Started process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "DIV_CAS.v"
Module <DIV_CAS> compiled
Compiling verilog file "DIV_row.v"
Module <DIV_row> compiled
Compiling verilog file "DIV.v"
Module <DIV> compiled
No errors in compilation
Analysis of file <"DIV.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <DIV>.
	width_a = 16
	width_b = 8
Module <DIV> is correct for synthesis.
 
Analyzing module <DIV_row>.
	width = 8
Module <DIV_row> is correct for synthesis.
 
Analyzing module <DIV_CAS>.
WARNING:Xst:905 - "DIV_CAS.v" line 35: The signals <b> are missing in the sensitivity list of always block.
Module <DIV_CAS> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <DIV_CAS>.
    Related source file is "DIV_CAS.v".
WARNING:Xst:646 - Signal <b> is assigned but never used.
    Found 1-bit xor3 for signal <s_out>.
    Summary:
	inferred   1 Xor(s).
Unit <DIV_CAS> synthesized.


Synthesizing Unit <DIV_row>.
    Related source file is "DIV_row.v".
Unit <DIV_row> synthesized.


Synthesizing Unit <DIV>.
    Related source file is "DIV.v".
WARNING:Xst:646 - Signal <s10<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s11<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s12<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s13<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s14<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s15<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s1<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s2<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s3<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s4<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s5<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s6<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s7<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s8<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s9<8>> is assigned but never used.
WARNING:Xst:737 - Found 8-bit latch for signal <r_out>.
WARNING:Xst:737 - Found 16-bit latch for signal <q_out>.
    Found 8-bit adder for signal <$n0001> created at line 37.
    Summary:
	inferred   1 Adder/Subtractor(s).
Unit <DIV> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 8-bit adder                       : 1
# Latches                          : 2
 16-bit latch                      : 1
 8-bit latch                       : 1
# Xors                             : 144
 1-bit xor3                        : 144

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <DIV> ...

Optimizing unit <DIV_CAS> ...
Loading device for application Rf_Device from file 'v100.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block DIV, actual ratio is 13.
PACKER Warning: Lut DIV__n0001<1>lut driving carry DIV__n0001<1>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v100pq240-4 

 Number of Slices:                     163  out of   1200    13%  
 Number of Slice Flip Flops:            24  out of   2400     1%  
 Number of 4 input LUTs:               283  out of   2400    11%  
 Number of bonded IOBs:                 49  out of    170    28%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
div_enable                         | BUFGP                  | 24    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: No path found
   Minimum input arrival time before clock: 335.072ns
   Maximum output required time after clock: 8.426ns
   Maximum combinational path delay: No path found

=========================================================================