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* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Analyzing FSM <FSM_0> for best encoding.Optimizing FSM <FSM_0> on signal <state[1:6]> with speed1 encoding.------------------- State | Encoding------------------- 000 | 001000 001 | 010000 010 | 000100 011 | 000001 100 | 000010 101 | 100000-------------------Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# FSMs : 1# Adders/Subtractors : 11 16-bit adder : 7 8-bit adder : 1 8-bit adder carry out : 2 9-bit subtractor : 1# Counters : 2 8-bit up counter : 1 8-bit updown counter : 1# Registers : 19 1-bit register : 5 8-bit register : 14# Latches : 3 16-bit latch : 2 8-bit latch : 1# Multiplexers : 9 1-bit 4-to-1 multiplexer : 3 2-bit 4-to-1 multiplexer : 1 8-bit 16-to-1 multiplexer : 1 8-bit 4-to-1 multiplexer : 3 8-bit 8-to-1 multiplexer : 1# Tristates : 1 8-bit tristate buffer : 1# Xors : 144 1-bit xor3 : 144==================================================================================================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1291 - FF/Latch <reg_out_7> is unconnected in block <C>.WARNING:Xst:1291 - FF/Latch <reg_out_1> is unconnected in block <C>.WARNING:Xst:1291 - FF/Latch <reg_out_2> is unconnected in block <C>.WARNING:Xst:1291 - FF/Latch <reg_out_3> is unconnected in block <C>.WARNING:Xst:1291 - FF/Latch <reg_out_4> is unconnected in block <C>.WARNING:Xst:1291 - FF/Latch <reg_out_5> is unconnected in block <C>.WARNING:Xst:1291 - FF/Latch <reg_out_6> is unconnected in block <C>.WARNING:Xst:1291 - FF/Latch <reg_out_7> is unconnected in block <Z>.WARNING:Xst:1291 - FF/Latch <reg_out_1> is unconnected in block <Z>.WARNING:Xst:1291 - FF/Latch <reg_out_2> is unconnected in block <Z>.WARNING:Xst:1291 - FF/Latch <reg_out_3> is unconnected in block <Z>.WARNING:Xst:1291 - FF/Latch <reg_out_4> is unconnected in block <Z>.WARNING:Xst:1291 - FF/Latch <reg_out_5> is unconnected in block <Z>.WARNING:Xst:1291 - FF/Latch <reg_out_6> is unconnected in block <Z>.Register <C/reg_out_4> equivalent to <C/reg_out_3> has been removedRegister <C/reg_out_5> equivalent to <C/reg_out_3> has been removedRegister <C/reg_out_6> equivalent to <C/reg_out_3> has been removedRegister <C/reg_out_2> equivalent to <C/reg_out_1> has been removedRegister <C/reg_out_3> equivalent to <C/reg_out_1> has been removedRegister <Z/reg_out_1> equivalent to <Z/reg_out_7> has been removedRegister <Z/reg_out_2> equivalent to <Z/reg_out_7> has been removedRegister <Z/reg_out_6> equivalent to <Z/reg_out_7> has been removedRegister <Z/reg_out_5> equivalent to <Z/reg_out_7> has been removedRegister <Z/reg_out_4> equivalent to <Z/reg_out_7> has been removedRegister <Z/reg_out_3> equivalent to <Z/reg_out_7> has been removedRegister <C/reg_out_1> equivalent to <C/reg_out_7> has been removedWARNING:Xst:1291 - FF/Latch <C/reg_out_7> is unconnected in block <CPU>.WARNING:Xst:1291 - FF/Latch <Z/reg_out_7> is unconnected in block <CPU>.Optimizing unit <CPU> ...Optimizing unit <DIV_CAS> ...Optimizing unit <mux2> ...Optimizing unit <DIV> ...Optimizing unit <CU> ...Optimizing unit <MUL> ...Optimizing unit <ALU> ...Optimizing unit <GR> ...Loading device for application Rf_Device from file 'v100.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block CPU, actual ratio is 37.FlipFlop CU/state_FFd2 has been replicated 1 time(s)FlipFlop CU/state_FFd4 has been replicated 2 time(s)FlipFlop CU/state_FFd5 has been replicated 2 time(s)FlipFlop IR/reg_out_3 has been replicated 2 time(s)FlipFlop IR/reg_out_4 has been replicated 3 time(s)FlipFlop IR/reg_out_5 has been replicated 2 time(s)FlipFlop IR/reg_out_6 has been replicated 1 time(s)FlipFlop IR/reg_out_7 has been replicated 2 time(s)PACKER Warning: Lut DIV/DIV__n0001<1>lut driving carry DIV/DIV__n0001<1>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0002<8>lut driving carry MUL/MUL__n0002<8>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0002<9>lut driving carry MUL/MUL__n0002<9>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0002<10>lut driving carry MUL/MUL__n0002<10>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0002<11>lut driving carry MUL/MUL__n0002<11>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0002<12>lut driving carry MUL/MUL__n0002<12>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0002<13>lut driving carry MUL/MUL__n0002<13>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0003<6>lut driving carry MUL/MUL__n0003<6>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0003<7>lut driving carry MUL/MUL__n0003<7>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0003<8>lut driving carry MUL/MUL__n0003<8>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0003<9>lut driving carry MUL/MUL__n0003<9>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0003<10>lut driving carry MUL/MUL__n0003<10>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0003<11>lut driving carry MUL/MUL__n0003<11>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0005<4>lut driving carry MUL/MUL__n0005<4>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0005<5>lut driving carry MUL/MUL__n0005<5>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0005<6>lut driving carry MUL/MUL__n0005<6>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0005<7>lut driving carry MUL/MUL__n0005<7>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0005<8>lut driving carry MUL/MUL__n0005<8>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0005<9>lut driving carry MUL/MUL__n0005<9>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0006<2>lut driving carry MUL/MUL__n0006<2>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0006<3>lut driving carry MUL/MUL__n0006<3>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0006<4>lut driving carry MUL/MUL__n0006<4>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0006<5>lut driving carry MUL/MUL__n0006<5>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0006<6>lut driving carry MUL/MUL__n0006<6>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0006<7>lut driving carry MUL/MUL__n0006<7>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0004<7>lut driving carry MUL/MUL__n0004<7>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0007<3>lut driving carry MUL/MUL__n0007<3>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0001<5>lut driving carry MUL/MUL__n0001<5>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.PACKER Warning: Lut MUL/MUL__n0001<6>lut driving carry MUL/MUL__n0001<6>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : v100pq240-4 Number of Slices: 472 out of 1200 39% Number of Slice Flip Flops: 174 out of 2400 7% Number of 4 input LUTs: 824 out of 2400 34% Number of bonded IOBs: 21 out of 170 12% Number of GCLKs: 3 out of 4 75% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 134 |DIVLE1(CU/DIVLE2:O) | BUFG(*)(DIV/q_out_6) | 24 |MULLE1(CU/MULLE2:O) | BUFG(*)(MUL/mul_out_2) | 16 |-----------------------------------+------------------------+-------+(*) These 2 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.Timing Summary:---------------Speed Grade: -4 Minimum period: 30.986ns (Maximum Frequency: 32.273MHz) Minimum input arrival time before clock: 11.839ns Maximum output required time after clock: 38.248ns Maximum combinational path delay: 14.695ns=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd c:\ttttt/_ngo -nt timestamp -ucfrtg.ucf -p xcv100-pq240-4 CPU.ngc CPU.ngd Reading NGO file 'C:/ttttt/CPU.ngc' ...Applying constraints in "frtg.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "CPU.ngd" ...Writing NGDBUILD log file "CPU.bld"...NGDBUILD done.
Started process "Map".Using target part "v100pq240-4".Mapping design into LUTs...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors: 0Number of warnings: 4Logic Utilization: Total Number Slice Registers: 174 out of 2,400 7% Number used as Flip Flops: 134 Number used as Latches: 40 Number of 4 input LUTs: 788 out of 2,400 32%Logic Distribution: Number of occupied Slices: 465 out of 1,200 38% Number of Slices containing only related logic: 465 out of 465 100% Number of Slices containing unrelated logic: 0 out of 465 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 808 out of 2,400 33% Number used as logic: 788 Number used as a route-thru: 20 Number of bonded IOBs: 20 out of 166 12% Number of GCLKs: 3 out of 4 75% Number of GCLKIOBs: 1 out of 4 25%Total equivalent gate count for design: 6,921Additional JTAG gate count for IOBs: 1,008Peak Memory Usage: 100 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Mapping completed.See MAP report file "CPU_map.mrp" for details.
Started process "Place & Route".Constraints file: CPU.pcf.Loading device for application Rf_Device from file 'v100.nph' in environmentC:/Xilinx. "CPU" is an NCD, version 3.1, device xcv100, package pq240, speed -4Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 125.000Celsius)Initializing voltage to 2.375 Volts. (default - Range: 2.375 to 2.625 Volts)Device speed data version: "FINAL 1.123 2005-01-22".Device Utilization Summary:⌨️ 快捷键说明
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