cpu.v

cup 的设计源代码

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    14:49:36 10/20/08
// Design Name:    
// Module Name:    CPU
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module CPU(data, address, CS, READ, WRITE, clk, rst);
    parameter width=8;

    inout[width-1:0] data;
    output[width-1:0] address;
    output CS;
    output READ;
    output WRITE;
    input clk;
    input rst;
    
    wire[width-1:0]data_in;
    wire[width-1:0]data_bus;
    wire[width-1:0]address;
    wire[width-1:0]GR_out;
    wire[width-1:0]ALU_out;
    wire[width-1:0]AC_out;
    wire[width-1:0]HAC_out;
    wire[width-1:0]AR_out;
    wire[width-1:0]IR_out;
    wire[width-1:0]PC_out;
    wire[width-1:0]SP_out;
    wire C_out;
    wire ALU_C;
    wire Z_out;
	 wire ALU_Z;  
    wire[width+width-1:0] MUL_out;
    wire[width+width-1:0] DIV_out;
    wire[width-1:0] MOD_out;
    wire[width-1:0] MUL_high_out;
    wire[width-1:0] MUL_low_out;
    wire[width-1:0] DIV_high_out;
    wire[width-1:0] DIV_low_out;
    
    
    wire[2:0]GR_address;
    wire[4:0]ALU_OP;
    
    wire MUL_sel;
    wire[1:0] C_sel;
    wire[1:0] DIV_sel;
    wire[1:0] AB_sel;
    wire[3:0] DB_sel;
    wire C_sel_out;
    wire[width-1:0] MUL_sel_out;
    wire[width-1:0] DIV_sel_out;
    
    wire CLE;
    wire ACLE;
    wire HACLE;
    wire ARLE;
    wire IRLE;
    wire PCLE;
    wire PCCE;
    wire SPIE;
    wire SPDE;
    wire GRLE;
    wire MULLE;
    wire DIVLE;
    
    assign data_in=data;
    assign data=(~CS && ~WRITE)?data_bus:8'bz;
    assign {MUL_high_out,MUL_low_out}=MUL_out;
    assign {DIV_high_out,DIV_low_out}=DIV_out;
    
    register C(.clk(clk), .rst(rst), .load_enable(CLE), .reg_in(C_sel_out), .reg_out(C_out));
    register Z(.clk(clk), .rst(rst), .load_enable(ZLE), .reg_in(ALU_Z), .reg_out(Z_out));
    register AC(.clk(clk), .rst(rst), .load_enable(ACLE), .reg_in(data_bus), .reg_out(AC_out));
    register HAC(.clk(clk), .rst(rst), .load_enable(HACLE), .reg_in(data_bus), .reg_out(HAC_out));
    register AR(.clk(clk), .rst(rst), .load_enable(ARLE), .reg_in(data_bus), .reg_out(AR_out));
    register IR(.clk(clk), .rst(rst), .load_enable(IRLE), .reg_in(data_bus), .reg_out(IR_out));
    
    mux2 MUX_2_MUL(.m0_in(MUL_low_out), .m1_in(MUL_high_out), .sel_in(MUL_sel), .mux2_out(MUL_sel_out));
    
    mux4 MUX_4_C(.m0_in(ALU_C), .m1_in(AC_out[0]), .m2_in(AC_out[7]), .m3_in(2'b00), .sel_in(C_sel), .mux4_out(C_sel_out));
    mux4 MUX_4_DIV(.m0_in(DIV_low_out), .m1_in(DIV_high_out), .m2_in(MOD_out), .m3_in(8'b0), .sel_in(DIV_sel), .mux4_out(DIV_sel_out));
    mux4 MUX_4_AB(.m0_in(SP_out), .m1_in(AR_out), .m2_in(PC_out), .m3_in(8'b0), .sel_in(AB_sel), .mux4_out(address));
    
    mux16 MUX_16_DB(.m0_in(AC_out), .m1_in(ALU_out), .m2_in(MUL_sel_out), .m3_in(DIV_sel_out), .m4_in(HAC_out), .m5_in(data_in), .m6_in(GR_out), .m7_in(PC_out), .m8_in(AR_out), 
                .m9_in(8'b0), .m10_in(8'b0), .m11_in(8'b0), .m12_in(8'b0), .m13_in(8'b0), .m14_in(8'b0), .m15_in(8'b0), 
                .sel_in(DB_sel), .mux16_out(data_bus));
    
    PC PC(.clk(clk), .rst(rst), .PC_in(data_bus), .load_enable(PCLE), .count_enable(PCCE), .PC_out(PC_out));
    
    SP SP(.clk(clk), .rst(rst), .inc_enable(SPIE), .dec_enable(SPDE), .SP_out(SP_out));
    
    GR GR(.clk(clk), .rst(rst), .GR_in(data_bus), .GR_address(GR_address), .load_enable(GRLE), .GR_out(GR_out));
    
    ALU ALU(.AC_in(AC_out), .C_in(C_out), .GR_in(GR_out), .op_in(ALU_OP), .ALU_out(ALU_out), .C_out(ALU_C), .Z_out(ALU_Z));

    MUL MUL(.a_in(AC_out), .b_in(GR_out), .mul_out(MUL_out), .mul_enable(MULLE));
    
    DIV DIV(.a_in({HAC_out,GR_out}), .b_in(AC_out), .div_enable(DIVLE), .q_out(DIV_out), .r_out(MOD_out));

    CU CU(.CLE(CLE), .ZLE(ZLE), .ACLE(ACLE), .HACLE(HACLE), .IRLE(IRLE), .MULLE(MULLE), .DIVLE(DIVLE), .C_SEL(C_sel), .MUL_SEL(MUL_sel), .DIV_SEL(DIV_sel), 
             .AB_SEL(AB_sel), .DB_SEL(DB_sel), .SPIE(SPIE), .SPDE(SPDE), .PCCE(PCCE), .CS(CS), .READ(READ), .WRITE(WRITE), .ALU_OP(ALU_OP),.PCLE(PCLE), .ARLE(ARLE), 
             .GR_ADDRESS(GR_address), .IR_OUT(IR_out), .C_OUT(C_out), .Z_OUT(Z_out), .CLK(clk), .RST(rst),.AR_OUT(AR_out),.GRLE(GRLE));
endmodule