cpu.twr

来自「cup 的设计源代码」· TWR 代码 · 共 84 行

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Release 7.1.04i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -ise c:\ttttt\ttttt.ise -intstyle ise -e 3 -l 3 -s 4
-xml CPU CPU.ncd -o CPU.twr CPU.pcf


Design file:              cpu.ncd
Physical constraint file: cpu.pcf
Device,speed:             xcv100,-4 (FINAL 1.123 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
data<0>     |   10.585(R)|   -2.192(R)|clk_BUFGP         |   0.000|
data<1>     |   10.876(R)|   -2.708(R)|clk_BUFGP         |   0.000|
data<2>     |   12.589(R)|   -3.638(R)|clk_BUFGP         |   0.000|
data<3>     |   14.286(R)|   -4.322(R)|clk_BUFGP         |   0.000|
data<4>     |   14.227(R)|   -4.844(R)|clk_BUFGP         |   0.000|
data<5>     |   11.720(R)|   -3.564(R)|clk_BUFGP         |   0.000|
data<6>     |   13.280(R)|   -4.091(R)|clk_BUFGP         |   0.000|
data<7>     |   10.884(R)|   -2.507(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
CS          |   23.822(R)|clk_BUFGP         |   0.000|
READ        |   20.262(R)|clk_BUFGP         |   0.000|
WRITE       |   18.315(R)|clk_BUFGP         |   0.000|
address<0>  |   25.040(R)|clk_BUFGP         |   0.000|
address<1>  |   25.959(R)|clk_BUFGP         |   0.000|
address<2>  |   25.290(R)|clk_BUFGP         |   0.000|
address<3>  |   25.009(R)|clk_BUFGP         |   0.000|
address<4>  |   24.530(R)|clk_BUFGP         |   0.000|
address<5>  |   25.037(R)|clk_BUFGP         |   0.000|
address<6>  |   25.703(R)|clk_BUFGP         |   0.000|
address<7>  |   25.765(R)|clk_BUFGP         |   0.000|
data<0>     |   36.464(R)|clk_BUFGP         |   0.000|
data<1>     |   38.287(R)|clk_BUFGP         |   0.000|
data<2>     |   39.795(R)|clk_BUFGP         |   0.000|
data<3>     |   41.311(R)|clk_BUFGP         |   0.000|
data<4>     |   41.144(R)|clk_BUFGP         |   0.000|
data<5>     |   40.621(R)|clk_BUFGP         |   0.000|
data<6>     |   41.963(R)|clk_BUFGP         |   0.000|
data<7>     |   41.089(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |   35.795|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Fri Nov 21 11:14:34 2008
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Peak Memory Usage: 73 MB