mux16.v

cup 的设计源代码

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    15:26:07 10/20/08
// Design Name:    
// Module Name:    mux16
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module mux16(m0_in, m1_in, m2_in, m3_in, m4_in, m5_in, m6_in, m7_in, m8_in, 
                m9_in, m10_in, m11_in, m12_in, m13_in, m14_in, m15_in, 
                sel_in, mux16_out);
    parameter width=8;            
                
    input[width-1:0] m0_in;
    input[width-1:0] m1_in;
    input[width-1:0] m2_in;
    input[width-1:0] m3_in;
    input[width-1:0] m4_in;
    input[width-1:0] m5_in;
    input[width-1:0] m6_in;
    input[width-1:0] m7_in;
    input[width-1:0] m8_in;
    input[width-1:0] m9_in;
    input[width-1:0] m10_in;
    input[width-1:0] m11_in;
    input[width-1:0] m12_in;
    input[width-1:0] m13_in;
    input[width-1:0] m14_in;
    input[width-1:0] m15_in;
    input[3:0] sel_in;
    output[width-1:0] mux16_out;
    
    reg[width-1:0] mux16_out;
    
    always@(m0_in or m1_in or m2_in or m3_in or m4_in or m5_in or m6_in or m7_in or m8_in or 
                m9_in or m10_in or m11_in or m12_in or m13_in or m14_in or m15_in or 
                sel_in)
    begin
        case(sel_in)
        'b0000:mux16_out=m0_in;
        'b0001:mux16_out=m1_in;
        'b0010:mux16_out=m2_in;
        'b0011:mux16_out=m3_in;
        'b0100:mux16_out=m4_in;
        'b0101:mux16_out=m5_in;
        'b0110:mux16_out=m6_in;
        'b0111:mux16_out=m7_in;
        'b1000:mux16_out=m8_in;
        'b1001:mux16_out=m9_in;
        'b1010:mux16_out=m10_in;
        'b1011:mux16_out=m11_in;
        'b1100:mux16_out=m12_in;
        'b1101:mux16_out=m13_in;
        'b1110:mux16_out=m14_in;
        'b1111:mux16_out=m15_in;
        endcase
    end


endmodule