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📄 div.syr

📁 cup 的设计源代码
💻 SYR
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#      BUFGP                       : 1# IO Buffers                       : 48#      IBUF                        : 24#      OBUF                        : 24=========================================================================Device utilization summary:---------------------------Selected Device : v100pq240-4  Number of Slices:                     163  out of   1200    13%   Number of Slice Flip Flops:            24  out of   2400     1%   Number of 4 input LUTs:               283  out of   2400    11%   Number of bonded IOBs:                 49  out of    170    28%   Number of GCLKs:                        1  out of      4    25%  =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+div_enable                         | BUFGP                  | 24    |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4   Minimum period: No path found   Minimum input arrival time before clock: 335.072ns   Maximum output required time after clock: 8.426ns   Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'div_enable'  Total number of paths / destination ports: 11693769377881610000 / 24-------------------------------------------------------------------------Offset:              335.072ns (Levels of Logic = 140)  Source:            b_in<0> (PAD)  Destination:       r_out_5 (LATCH)  Destination Clock: div_enable falling  Data Path: b_in<0> to r_out_5                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     IBUF:I->O            38   0.989   4.510  b_in_0_IBUF (b_in_0_IBUF)     LUT4:I0->O            3   0.738   1.628  row1/CAS2/c_out1 (row1/c3)     LUT3:I0->O            3   0.738   1.628  row1/CAS4/c_out1 (row1/c5)     LUT3:I0->O            4   0.738   1.760  row1/CAS6/c_out1 (row1/c7)     LUT4:I1->O            2   0.738   1.474  row2/CAS0/c_out11 (row2/c1)     LUT4:I0->O            2   0.738   1.474  row2/CAS1/c_out1 (row2/c2)     LUT4:I0->O            2   0.738   1.474  row2/CAS2/c_out1 (row2/c3)     LUT4:I0->O            2   0.738   1.474  row2/CAS3/c_out1 (row2/c4)     LUT4:I0->O            2   0.738   1.474  row2/CAS4/c_out1 (row2/c5)     LUT4:I0->O            2   0.738   1.474  row2/CAS5/c_out1 (row2/c6)     LUT4:I0->O            3   0.738   1.628  row2/CAS6/c_out1 (row2/c7)     LUT4:I0->O           16   0.738   3.080  row2/CAS8/c_out1 (q<14>)     LUT3:I2->O            2   0.738   1.474  row3/CAS0/c_out11 (row3/c1)     LUT4:I0->O            2   0.738   1.474  row3/CAS1/c_out1 (row3/c2)     LUT4:I0->O            2   0.738   1.474  row3/CAS2/c_out1 (row3/c3)     LUT4:I0->O            2   0.738   1.474  row3/CAS3/c_out1 (row3/c4)     LUT4:I0->O            2   0.738   1.474  row3/CAS4/c_out1 (row3/c5)     LUT4:I0->O            2   0.738   1.474  row3/CAS5/c_out1 (row3/c6)     LUT4:I0->O            2   0.738   1.474  row3/CAS6/c_out1 (row3/c7)     LUT4:I0->O            2   0.738   1.474  row3/CAS7/c_out1 (row3/c8)     LUT4:I0->O            1   0.738   0.000  row3/CAS8/c_out1_F (N32)     MUXF5:I0->O          17   0.562   3.190  row3/CAS8/c_out1 (q<13>)     LUT3:I2->O            2   0.738   1.474  row4/CAS0/c_out11 (row4/c1)     LUT4:I0->O            2   0.738   1.474  row4/CAS1/c_out1 (row4/c2)     LUT4:I0->O            2   0.738   1.474  row4/CAS2/c_out1 (row4/c3)     LUT4:I0->O            2   0.738   1.474  row4/CAS3/c_out1 (row4/c4)     LUT4:I0->O            2   0.738   1.474  row4/CAS4/c_out1 (row4/c5)     LUT4:I0->O            2   0.738   1.474  row4/CAS5/c_out1 (row4/c6)     LUT4:I0->O            2   0.738   1.474  row4/CAS6/c_out1 (row4/c7)     LUT4:I0->O            1   0.738   1.265  row4/CAS7/c_out1 (row4/c8)     LUT4:I0->O           17   0.738   3.190  row4/CAS8/c_out1 (q<12>)     LUT3:I2->O            2   0.738   1.474  row5/CAS0/c_out11 (row5/c1)     LUT4:I0->O            2   0.738   1.474  row5/CAS1/c_out1 (row5/c2)     LUT4:I0->O            2   0.738   1.474  row5/CAS2/c_out1 (row5/c3)     LUT4:I0->O            2   0.738   1.474  row5/CAS3/c_out1 (row5/c4)     LUT4:I0->O            2   0.738   1.474  row5/CAS4/c_out1 (row5/c5)     LUT4:I0->O            2   0.738   1.474  row5/CAS5/c_out1 (row5/c6)     LUT4:I0->O            2   0.738   1.474  row5/CAS6/c_out1 (row5/c7)     LUT4:I0->O            1   0.738   1.265  row5/CAS7/c_out1 (row5/c8)     LUT4:I0->O           17   0.738   3.190  row5/CAS8/c_out1 (q<11>)     LUT3:I2->O            2   0.738   1.474  row6/CAS0/c_out11 (row6/c1)     LUT4:I0->O            2   0.738   1.474  row6/CAS1/c_out1 (row6/c2)     LUT4:I0->O            2   0.738   1.474  row6/CAS2/c_out1 (row6/c3)     LUT4:I0->O            2   0.738   1.474  row6/CAS3/c_out1 (row6/c4)     LUT4:I0->O            2   0.738   1.474  row6/CAS4/c_out1 (row6/c5)     LUT4:I0->O            2   0.738   1.474  row6/CAS5/c_out1 (row6/c6)     LUT4:I0->O            2   0.738   1.474  row6/CAS6/c_out1 (row6/c7)     LUT4:I0->O            1   0.738   1.265  row6/CAS7/c_out1 (row6/c8)     LUT4:I0->O           17   0.738   3.190  row6/CAS8/c_out1 (q<10>)     LUT3:I2->O            2   0.738   1.474  row7/CAS0/c_out11 (row7/c1)     LUT4:I0->O            2   0.738   1.474  row7/CAS1/c_out1 (row7/c2)     LUT4:I0->O            2   0.738   1.474  row7/CAS2/c_out1 (row7/c3)     LUT4:I0->O            2   0.738   1.474  row7/CAS3/c_out1 (row7/c4)     LUT4:I0->O            2   0.738   1.474  row7/CAS4/c_out1 (row7/c5)     LUT4:I0->O            2   0.738   1.474  row7/CAS5/c_out1 (row7/c6)     LUT4:I0->O            2   0.738   1.474  row7/CAS6/c_out1 (row7/c7)     LUT4:I0->O            1   0.738   1.265  row7/CAS7/c_out1 (row7/c8)     LUT4:I0->O           17   0.738   3.190  row7/CAS8/c_out1 (q<9>)     LUT3:I2->O            2   0.738   1.474  row8/CAS0/c_out11 (row8/c1)     LUT4:I0->O            2   0.738   1.474  row8/CAS1/c_out1 (row8/c2)     LUT4:I0->O            2   0.738   1.474  row8/CAS2/c_out1 (row8/c3)     LUT4:I0->O            2   0.738   1.474  row8/CAS3/c_out1 (row8/c4)     LUT4:I0->O            2   0.738   1.474  row8/CAS4/c_out1 (row8/c5)     LUT4:I0->O            2   0.738   1.474  row8/CAS5/c_out1 (row8/c6)     LUT4:I0->O            2   0.738   1.474  row8/CAS6/c_out1 (row8/c7)     LUT4:I0->O            1   0.738   1.265  row8/CAS7/c_out1 (row8/c8)     LUT4:I0->O           17   0.738   3.190  row8/CAS8/c_out1 (q<8>)     LUT3:I2->O            2   0.738   1.474  row9/CAS0/c_out11 (row9/c1)     LUT4:I0->O            2   0.738   1.474  row9/CAS1/c_out1 (row9/c2)     LUT4:I0->O            2   0.738   1.474  row9/CAS2/c_out1 (row9/c3)     LUT4:I0->O            2   0.738   1.474  row9/CAS3/c_out1 (row9/c4)     LUT4:I0->O            2   0.738   1.474  row9/CAS4/c_out1 (row9/c5)     LUT4:I0->O            2   0.738   1.474  row9/CAS5/c_out1 (row9/c6)     LUT4:I0->O            2   0.738   1.474  row9/CAS6/c_out1 (row9/c7)     LUT4:I0->O            1   0.738   1.265  row9/CAS7/c_out1 (row9/c8)     LUT4:I0->O           17   0.738   3.190  row9/CAS8/c_out1 (q<7>)     LUT3:I2->O            2   0.738   1.474  row10/CAS0/c_out11 (row10/c1)     LUT4:I0->O            2   0.738   1.474  row10/CAS1/c_out1 (row10/c2)     LUT4:I0->O            2   0.738   1.474  row10/CAS2/c_out1 (row10/c3)     LUT4:I0->O            2   0.738   1.474  row10/CAS3/c_out1 (row10/c4)     LUT4:I0->O            2   0.738   1.474  row10/CAS4/c_out1 (row10/c5)     LUT4:I0->O            2   0.738   1.474  row10/CAS5/c_out1 (row10/c6)     LUT4:I0->O            2   0.738   1.474  row10/CAS6/c_out1 (row10/c7)     LUT4:I0->O            1   0.738   1.265  row10/CAS7/c_out1 (row10/c8)     LUT4:I0->O           17   0.738   3.190  row10/CAS8/c_out1 (q<6>)     LUT3:I2->O            2   0.738   1.474  row11/CAS0/c_out11 (row11/c1)     LUT4:I0->O            2   0.738   1.474  row11/CAS1/c_out1 (row11/c2)     LUT4:I0->O            2   0.738   1.474  row11/CAS2/c_out1 (row11/c3)     LUT4:I0->O            2   0.738   1.474  row11/CAS3/c_out1 (row11/c4)     LUT4:I0->O            2   0.738   1.474  row11/CAS4/c_out1 (row11/c5)     LUT4:I0->O            2   0.738   1.474  row11/CAS5/c_out1 (row11/c6)     LUT4:I0->O            2   0.738   1.474  row11/CAS6/c_out1 (row11/c7)     LUT4:I0->O            1   0.738   1.265  row11/CAS7/c_out1 (row11/c8)     LUT4:I0->O           17   0.738   3.190  row11/CAS8/c_out1 (q<5>)     LUT3:I2->O            2   0.738   1.474  row12/CAS0/c_out11 (row12/c1)     LUT4:I0->O            2   0.738   1.474  row12/CAS1/c_out1 (row12/c2)     LUT4:I0->O            2   0.738   1.474  row12/CAS2/c_out1 (row12/c3)     LUT4:I0->O            2   0.738   1.474  row12/CAS3/c_out1 (row12/c4)     LUT4:I0->O            2   0.738   1.474  row12/CAS4/c_out1 (row12/c5)     LUT4:I0->O            2   0.738   1.474  row12/CAS5/c_out1 (row12/c6)     LUT4:I0->O            2   0.738   1.474  row12/CAS6/c_out1 (row12/c7)     LUT4:I0->O            1   0.738   1.265  row12/CAS7/c_out1 (row12/c8)     LUT4:I0->O           17   0.738   3.190  row12/CAS8/c_out1 (q<4>)     LUT3:I2->O            2   0.738   1.474  row13/CAS0/c_out11 (row13/c1)     LUT4:I0->O            2   0.738   1.474  row13/CAS1/c_out1 (row13/c2)     LUT4:I0->O            2   0.738   1.474  row13/CAS2/c_out1 (row13/c3)     LUT4:I0->O            2   0.738   1.474  row13/CAS3/c_out1 (row13/c4)     LUT4:I0->O            2   0.738   1.474  row13/CAS4/c_out1 (row13/c5)     LUT4:I0->O            2   0.738   1.474  row13/CAS5/c_out1 (row13/c6)     LUT4:I0->O            2   0.738   1.474  row13/CAS6/c_out1 (row13/c7)     LUT4:I0->O            1   0.738   1.265  row13/CAS7/c_out1 (row13/c8)     LUT4:I0->O           17   0.738   3.190  row13/CAS8/c_out1 (q<3>)     LUT3:I2->O            2   0.738   1.474  row14/CAS0/c_out11 (row14/c1)     LUT4:I0->O            2   0.738   1.474  row14/CAS1/c_out1 (row14/c2)     LUT4:I0->O            2   0.738   1.474  row14/CAS2/c_out1 (row14/c3)     LUT4:I0->O            2   0.738   1.474  row14/CAS3/c_out1 (row14/c4)     LUT4:I0->O            2   0.738   1.474  row14/CAS4/c_out1 (row14/c5)     LUT4:I0->O            2   0.738   1.474  row14/CAS5/c_out1 (row14/c6)     LUT4:I0->O            2   0.738   1.474  row14/CAS6/c_out1 (row14/c7)     LUT4:I0->O            1   0.738   1.265  row14/CAS7/c_out1 (row14/c8)     LUT4:I0->O           17   0.738   3.190  row14/CAS8/c_out1 (q<2>)     LUT3:I2->O            2   0.738   1.474  row15/CAS0/c_out11 (row15/c1)     LUT4:I0->O            2   0.738   1.474  row15/CAS1/c_out1 (row15/c2)     LUT4:I0->O            2   0.738   1.474  row15/CAS2/c_out1 (row15/c3)     LUT4:I0->O            2   0.738   1.474  row15/CAS3/c_out1 (row15/c4)     LUT4:I0->O            2   0.738   1.474  row15/CAS4/c_out1 (row15/c5)     LUT4:I0->O            2   0.738   1.474  row15/CAS5/c_out1 (row15/c6)     LUT4:I0->O            2   0.738   1.474  row15/CAS6/c_out1 (row15/c7)     LUT4:I0->O            1   0.738   1.265  row15/CAS7/c_out1 (row15/c8)     LUT4:I0->O           25   0.738   3.795  row15/CAS8/c_out1 (q<1>)     LUT3:I2->O            2   0.738   1.474  row16/CAS0/c_out11 (row16/c1)     LUT4:I0->O            3   0.738   1.628  row16/CAS1/c_out1 (row16/c2)     LUT4:I0->O            3   0.738   1.628  row16/CAS2/c_out1 (row16/c3)     LUT4:I0->O            3   0.738   1.628  row16/CAS3/c_out1 (row16/c4)     LUT4:I0->O            3   0.738   1.628  row16/CAS4/c_out1 (row16/c5)     LUT4:I0->O            3   0.738   1.628  row16/CAS5/c_out1 (row16/c6)     LUT4:I0->O            3   0.738   1.628  row16/CAS6/c_out1 (row16/c7)     LUT4:I0->O            2   0.738   1.474  row16/CAS7/c_out1 (row16/c8)     LUT4:I2->O            8   0.738   2.255  row16/CAS8/Mxor_s_out_Xo<1>1 (s16<8>)     LUT3:I1->O            1   0.738   0.000  _n0000<7>1 (_n0000<7>)     LD:D                      0.765          r_out_7    ----------------------------------------    Total                    335.072ns (104.161ns logic, 230.912ns route)                                       (31.1% logic, 68.9% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'div_enable'  Total number of paths / destination ports: 24 / 24-------------------------------------------------------------------------Offset:              8.426ns (Levels of Logic = 1)  Source:            q_out_15 (LATCH)  Destination:       q_out<15> (PAD)  Source Clock:      div_enable falling  Data Path: q_out_15 to q_out<15>                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     LD:G->Q               1   1.509   1.265  q_out_15 (q_out_15)     OBUF:I->O                 5.652          q_out_15_OBUF (q_out<15>)    ----------------------------------------    Total                      8.426ns (7.161ns logic, 1.265ns route)                                       (85.0% logic, 15.0% route)=========================================================================CPU : 4.20 / 4.92 s | Elapsed : 4.00 / 4.00 s --> Total memory usage is 87784 kilobytesNumber of errors   :    0 (   0 filtered)Number of warnings :   19 (   0 filtered)Number of infos    :    0 (   0 filtered)

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