div.syr

cup 的设计源代码

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: DIV.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "DIV.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "DIV"
Output Format                      : NGC
Target Device                      : xcv100-4-pq240

---- Source Options
Top Module Name                    : DIV
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : DIV.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "DIV_CAS.v"
Module <DIV_CAS> compiled
Compiling verilog file "DIV_row.v"
Module <DIV_row> compiled
Compiling verilog file "DIV.v"
Module <DIV> compiled
No errors in compilation
Analysis of file <"DIV.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <DIV>.
	width_a = 16
	width_b = 8
Module <DIV> is correct for synthesis.
 
Analyzing module <DIV_row>.
	width = 8
Module <DIV_row> is correct for synthesis.
 
Analyzing module <DIV_CAS>.
WARNING:Xst:905 - "DIV_CAS.v" line 35: The signals <b> are missing in the sensitivity list of always block.
Module <DIV_CAS> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <DIV_CAS>.
    Related source file is "DIV_CAS.v".
WARNING:Xst:646 - Signal <b> is assigned but never used.
    Found 1-bit xor3 for signal <s_out>.
    Summary:
	inferred   1 Xor(s).
Unit <DIV_CAS> synthesized.


Synthesizing Unit <DIV_row>.
    Related source file is "DIV_row.v".
Unit <DIV_row> synthesized.


Synthesizing Unit <DIV>.
    Related source file is "DIV.v".
WARNING:Xst:646 - Signal <s10<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s11<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s12<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s13<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s14<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s15<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s1<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s2<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s3<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s4<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s5<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s6<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s7<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s8<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s9<8>> is assigned but never used.
WARNING:Xst:737 - Found 8-bit latch for signal <r_out>.
WARNING:Xst:737 - Found 16-bit latch for signal <q_out>.
    Found 8-bit adder for signal <$n0001> created at line 37.
    Summary:
	inferred   1 Adder/Subtractor(s).
Unit <DIV> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 8-bit adder                       : 1
# Latches                          : 2
 16-bit latch                      : 1
 8-bit latch                       : 1
# Xors                             : 144
 1-bit xor3                        : 144

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <DIV> ...

Optimizing unit <DIV_CAS> ...
Loading device for application Rf_Device from file 'v100.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block DIV, actual ratio is 13.
PACKER Warning: Lut DIV__n0001<1>lut driving carry DIV__n0001<1>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : DIV.ngr
Top Level Output File Name         : DIV
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 49

Macro Statistics :
# Adders/Subtractors               : 1
#      8-bit adder                 : 1
# Xors                             : 144
#      1-bit xor3                  : 144

Cell Usage :
# BELS                             : 299
#      GND                         : 1
#      LUT2                        : 18
#      LUT3                        : 33
#      LUT4                        : 232
#      MUXCY                       : 7
#      MUXF5                       : 1
#      XORCY                       : 7
# FlipFlops/Latches                : 24
#      LD                          : 24
# Clock Buffers                    : 1