div_cas.v

来自「cup 的设计源代码」· Verilog 代码 · 共 47 行

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    18:57:37 10/11/08
// Design Name:    
// Module Name:    DIV_CAS
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module DIV_CAS(a_in, b_in, c_in, p_in, s_out, b_out, c_out, p_out);
    input a_in;
    input b_in;
    input c_in;
    input p_in;
    output s_out;
    output b_out;
    output c_out;
    output p_out;
    
    reg s_out,b_out,c_out,p_out;
    reg b;

    always@(a_in or b_in or c_in or p_in)
    begin
        if(p_in)
            b=~b_in;
        else
            b=b_in;
        s_out=c_in^a_in^b;         
        b_out=b_in;
        c_out=(a_in&b)|(a_in&c_in)|(b&c_in);
        p_out=p_in;
    end

endmodule