cu.v

cup 的设计源代码

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    15:25:55 10/15/08
// Design Name:    
// Module Name:    cu
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module CU(CLE, ZLE, ACLE, HACLE, IRLE, MULLE, DIVLE, C_SEL, MUL_SEL, DIV_SEL, 
             AB_SEL, DB_SEL, SPIE, SPDE, PCCE, CS, READ, WRITE, ALU_OP,PCLE, ARLE, 
             GR_ADDRESS, IR_OUT, C_OUT, Z_OUT, CLK, RST,AR_OUT,GRLE);
    output CLE;	   reg  CLE;			//CLE ?1b,C?????
    output ZLE;		reg  ZLE;	  
    output ACLE;		reg  ACLE;
    output HACLE;		reg  HACLE;
    output IRLE;		reg  IRLE;
    output MULLE;		reg  MULLE;
    output DIVLE;		reg  DIVLE;
	 output PCLE;	reg PCLE;
	 output ARLE;	reg ARLE;
    output [1:0] C_SEL;		 reg  [1:0] C_SEL;	
    output MUL_SEL;			 reg  MUL_SEL;
    output [1:0] DIV_SEL;	 reg  [1:0] DIV_SEL;
    output [1:0] AB_SEL;	 reg  [1:0] AB_SEL;
    output [3:0] DB_SEL;	 reg  [3:0] DB_SEL;
    output SPIE;				 reg  SPIE;
    output SPDE;				 reg  SPDE;
    output PCCE;				 reg  PCCE;
    output CS;					 reg  CS;
    output READ;				 reg  READ;
    output WRITE;				 reg  WRITE;
    output [4:0] ALU_OP;		reg  [4:0] ALU_OP;
    output [2:0] GR_ADDRESS;	  reg   [2:0] GR_ADDRESS;
	 output GRLE;			reg GRLE;
    input [7:0] IR_OUT;		 
    input C_OUT;
    input Z_OUT;
    input CLK;
    input RST;
	 input [7:0] AR_OUT;  //? AR ?????

parameter  FIRST ='b000,SECOND ='b001,THIRD = 'b010,HALT = 'b011,FORTH = 'b100,FIFTH='b101;

parameter SP_START='b1111_1111;	//????????


reg [2:0] state;  //????

always @ (posedge CLK  or  negedge RST)	//???
begin
	if(!RST)
		state <=FIFTH;
	else  
	begin
			case(state)
				FIRST:	state <=SECOND;
				SECOND:	state <=THIRD;
				THIRD :	state <=FORTH;
				FORTH : state <=FIFTH;
				FIFTH :
				begin
					if(IR_OUT[7:3]=='b01000)
						state <= HALT;
					else
						state <= FIRST;
				end
				HALT:	state <= HALT;
			endcase
	end
end

always @ (state or C_OUT or Z_OUT or IR_OUT or AR_OUT)
begin
	ZLE = 'b0;
	ALU_OP =	'b0;
	ACLE = 'b0;
	GR_ADDRESS = 'b0;
	GRLE = 'b0;	IRLE = 'b0;
	ARLE = 'b0;
	PCLE = 'b0;
	PCCE = 'b0;
	HACLE = 'b0;
	MULLE = 'b0;
	DIVLE = 'b0;
	C_SEL ='b0;
	MUL_SEL = 'b0;
	DIV_SEL ='b0;
	AB_SEL = 'b0;
	DB_SEL = 'b0;
	SPIE = 'b0;
	SPDE = 'b0;
	PCCE = 'b0;
	CS = 'b0;			 //?????
	READ ='b0;			 //?????
	WRITE ='b1;			 //?????
	ALU_OP = 'b0;
	GR_ADDRESS = 'b0;

	case(state)
	FIRST:
		begin
			CS ='b0;
			AB_SEL = 'b10;
			DB_SEL = 'b0101;
			IRLE = 'b1;
			PCCE = 'b1;
		end
	SECOND:
		begin		
		if(IR_OUT[7:3] =='b00010||IR_OUT[7:3]=='b00011)
		begin
				CS = 'b1;
		   	if(IR_OUT[7:3] =='b00010)
		   	begin
		   	   DB_SEL='b0100;
		   	   ACLE ='b1;
		   	end
		   	if(IR_OUT[7:3]=='b00011)
		   	begin
		   	   DB_SEL='b0000;
		   	   HACLE='b1;
		   	end
		end
		else
		begin
		if(IR_OUT[7:6]=='b01)
		begin	
				CS = 'b1;		
				if(IR_OUT[7:3]!='b01000&&IR_OUT[7:3]!='b01111)
				begin			
					ALU_OP = IR_OUT[7:3];
					DB_SEL = 'b0001;
					ACLE = 'b1;
					CLE = 'b1;
					ZLE = 'b1;
					if(IR_OUT[7:3]=='b01010)//SHCR
						C_SEL = 'b01;
					if(IR_OUT[7:3]=='b01100)//SHCL
						C_SEL = 'b10;
				end
				if(IR_OUT[7:3]=='b01111) //RET
					SPIE = 'b1;
		end
		else
		begin
				if(IR_OUT[7:3]=='b10011||IR_OUT[7:3]=='b10100||IR_OUT[7:3]=='b10101)		//JMP JNC JNZ
				begin
            		if(IR_OUT[7:3]=='b10100&&C_OUT!='b0||IR_OUT[7:3]=='b10101&&Z_OUT!='b0)
					begin	
						CS = 'b1;						 
						PCCE = 'b1;
					end
					else
					begin
						CS ='b0;
						AB_SEL = 'b10;
						DB_SEL = 'b0101;
						PCLE = 'b1;
					end
				end
				else
				begin
				   CS ='b0;
               AB_SEL = 'b10;
               DB_SEL = 'b0101;
               PCCE = 'b1;
               ARLE = 'b1;						
					if(IR_OUT[7:3]=='b10001||IR_OUT[2:0]== 'b10111||IR_OUT[2:0]== 'b11001)	  //POP  POPAC POPHAC
					begin
						SPIE = 'b1;
					end
				end									
		end
		end
		end
	THIRD:
		begin	
			if(IR_OUT[7:3]=='b00000||IR_OUT[7:3]=='b00001) 		  //LOAD  STORE
			begin
				if(IR_OUT[2:0]=='b001)		 //??驞LOAD 2?驞