mul.v

cup 的设计源代码

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    20:55:53 10/08/08
// Design Name:    
// Module Name:    MUL
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module MUL(a_in, b_in, mul_out, mul_enable);
	parameter width=8;

    input[width-1:0] a_in;
    input[width-1:0] b_in;	       
    input mul_enable;

	output[width+width-1:0] mul_out;
    
    assign mul_out=(mul_enable)?
                    (
                    16'b0+
                    ((b_in[0])?a_in[width-1:0]:16'b0)+
                    ((b_in[1])?{a_in[width-1:0],1'b0}:16'b0)+
                    ((b_in[2])?{a_in[width-1:0],2'b0}:16'b0)+
                    ((b_in[3])?{a_in[width-1:0],3'b0}:16'b0)+
                    ((b_in[4])?{a_in[width-1:0],4'b0}:16'b0)+
                    ((b_in[5])?{a_in[width-1:0],5'b0}:16'b0)+
                    ((b_in[6])?{a_in[width-1:0],6'b0}:16'b0)+
                    ((b_in[7])?{a_in[width-1:0],7'b0}:16'b0)                    
                    )
                    :mul_out;

endmodule