cpu.syr

cup 的设计源代码

Cell Usage :
# BELS                             : 1112
#      GND                         : 1
#      INV                         : 3
#      LUT1                        : 13
#      LUT2                        : 105
#      LUT2_D                      : 5
#      LUT2_L                      : 1
#      LUT3                        : 80
#      LUT3_D                      : 6
#      LUT3_L                      : 42
#      LUT4                        : 448
#      LUT4_D                      : 36
#      LUT4_L                      : 88
#      MUXCY                       : 108
#      MUXF5                       : 60
#      MUXF6                       : 12
#      VCC                         : 1
#      XORCY                       : 103
# FlipFlops/Latches                : 174
#      FDC                         : 9
#      FDCE                        : 108
#      FDCPE                       : 8
#      FDP                         : 1
#      FDPE                        : 8
#      LD                          : 40
# Clock Buffers                    : 3
#      BUFG                        : 2
#      BUFGP                       : 1
# IO Buffers                       : 20
#      IBUF                        : 1
#      IOBUF                       : 8
#      OBUF                        : 11
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v100pq240-4 

 Number of Slices:                     472  out of   1200    39%  
 Number of Slice Flip Flops:           174  out of   2400     7%  
 Number of 4 input LUTs:               824  out of   2400    34%  
 Number of bonded IOBs:                 21  out of    170    12%  
 Number of GCLKs:                        3  out of      4    75%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 134   |
DIVLE1(CU/DIVLE2:O)                | BUFG(*)(DIV/q_out_6)   | 24    |
MULLE1(CU/MULLE2:O)                | BUFG(*)(MUL/mul_out_2) | 16    |
-----------------------------------+------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 30.986ns (Maximum Frequency: 32.273MHz)
   Minimum input arrival time before clock: 11.839ns
   Maximum output required time after clock: 38.248ns
   Maximum combinational path delay: 14.695ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 30.986ns (frequency: 32.273MHz)
  Total number of paths / destination ports: 567796 / 257
-------------------------------------------------------------------------
Delay:               30.986ns (Levels of Logic = 20)
  Source:            IR/reg_out_1 (FF)
  Destination:       PC/PC_out_7 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: IR/reg_out_1 to PC/PC_out_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            19   1.372   3.410  IR/reg_out_1 (IR/reg_out_1)
     LUT3:I1->O            2   0.738   1.474  CU/Ker511 (CU/N51)
     LUT4_L:I3->LO         1   0.738   0.100  CU/Ker10732 (CHOICE2473)
     LUT4:I1->O            4   0.738   1.760  CU/Ker10762 (CHOICE2477)
     LUT4_D:I1->O          1   0.738   1.265  CU/GR_ADDRESS<1>1_SW0 (N1731)
     LUT4_D:I0->O         21   0.738   3.575  CU/GR_ADDRESS<1>1 (GR_address<1>)
     MUXF5:S->O            3   0.820   1.628  GR/GR_address<1>_rn_21 (GR/MUX_BLOCK_GR_address<1>_MUXF53)
     LUT4_L:I2->LO         1   0.738   0.000  ALU/ALU__n0001<1>lut (ALU/N15)
     MUXCY:S->O            1   0.842   0.000  ALU/ALU__n0001<1>cy (ALU/ALU__n0001<1>_cyo)
     MUXCY:CI->O           1   0.057   0.000  ALU/ALU__n0001<2>cy (ALU/ALU__n0001<2>_cyo)
     MUXCY:CI->O           1   0.057   0.000  ALU/ALU__n0001<3>cy (ALU/ALU__n0001<3>_cyo)
     XORCY:CI->O           1   0.538   1.265  ALU/ALU__n0001<4>_xor (ALU/_n0001<4>)
     LUT4:I2->O            2   0.738   1.474  ALU/ALU_out<4>31 (CHOICE2521)
     LUT4_L:I1->LO         1   0.738   0.000  DB_sel<0>19 (MUX_BLOCK_N30)
     MUXF5:I0->O           1   0.562   0.000  DB_sel<1>_rn_8 (MUX_BLOCK_DB_sel<1>_MUXF59)
     MUXF6:I0->O           2   0.412   1.474  DB_sel<2>_rn_3 (MUX_BLOCK_DB_sel<2>_MUXF64)
     LUT3_L:I0->LO         1   0.738   0.000  PC/PC_out_inst_lut3_41 (PC/PC_out_inst_lut3_4)
     MUXCY:S->O            1   0.842   0.000  PC/PC_out_inst_cy_5 (PC/PC_out_inst_cy_5)
     MUXCY:CI->O           1   0.057   0.000  PC/PC_out_inst_cy_6 (PC/PC_out_inst_cy_6)
     MUXCY:CI->O           0   0.057   0.000  PC/PC_out_inst_cy_7 (PC/PC_out_inst_cy_7)
     XORCY:CI->O           1   0.538   0.000  PC/PC_out_inst_sum_7 (PC/PC_out_inst_sum_7)
     FDCPE:D                   0.765          PC/PC_out_7
    ----------------------------------------
    Total                     30.986ns (13.561ns logic, 17.425ns route)
                                       (43.8% logic, 56.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 142 / 114
-------------------------------------------------------------------------
Offset:              11.839ns (Levels of Logic = 14)
  Source:            data<0> (PAD)
  Destination:       PC/PC_out_7 (FF)
  Destination Clock: clk rising

  Data Path: data<0> to PC/PC_out_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O           1   0.989   1.265  data_0_IOBUF (N1548)
     LUT3_L:I2->LO         1   0.738   0.000  DB_sel<0>1 (MUX_BLOCK_N2)
     MUXF5:I0->O           1   0.562   0.000  DB_sel<1> (MUX_BLOCK_DB_sel<1>_MUXF5)
     MUXF6:I1->O           1   0.307   1.265  DB_sel<2> (MUX_BLOCK_DB_sel<2>_MUXF6)
     LUT4_D:I3->O         13   0.738   2.750  DB_sel<3>8 (data_bus<0>)
     LUT3_L:I2->LO         1   0.738   0.000  PC/PC_out_inst_lut3_01 (PC/PC_out_inst_lut3_0)
     MUXCY:S->O            1   0.842   0.000  PC/PC_out_inst_cy_1 (PC/PC_out_inst_cy_1)
     MUXCY:CI->O           1   0.057   0.000  PC/PC_out_inst_cy_2 (PC/PC_out_inst_cy_2)
     MUXCY:CI->O           1   0.057   0.000  PC/PC_out_inst_cy_3 (PC/PC_out_inst_cy_3)
     MUXCY:CI->O           1   0.057   0.000  PC/PC_out_inst_cy_4 (PC/PC_out_inst_cy_4)
     MUXCY:CI->O           1   0.057   0.000  PC/PC_out_inst_cy_5 (PC/PC_out_inst_cy_5)
     MUXCY:CI->O           1   0.057   0.000  PC/PC_out_inst_cy_6 (PC/PC_out_inst_cy_6)
     MUXCY:CI->O           0   0.057   0.000  PC/PC_out_inst_cy_7 (PC/PC_out_inst_cy_7)
     XORCY:CI->O           1   0.538   0.000  PC/PC_out_inst_sum_7 (PC/PC_out_inst_sum_7)
     FDCPE:D                   0.765          PC/PC_out_7
    ----------------------------------------
    Total                     11.839ns (6.559ns logic, 5.280ns route)
                                       (55.4% logic, 44.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 31402 / 19
-------------------------------------------------------------------------
Offset:              38.248ns (Levels of Logic = 21)
  Source:            IR/reg_out_1 (FF)
  Destination:       data<7> (PAD)
  Source Clock:      clk rising

  Data Path: IR/reg_out_1 to data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            19   1.372   3.410  IR/reg_out_1 (IR/reg_out_1)
     LUT3:I1->O            2   0.738   1.474  CU/Ker511 (CU/N51)
     LUT4_L:I3->LO         1   0.738   0.100  CU/Ker10732 (CHOICE2473)
     LUT4:I1->O            4   0.738   1.760  CU/Ker10762 (CHOICE2477)
     LUT4_D:I1->O          1   0.738   1.265  CU/GR_ADDRESS<1>1_SW0 (N1731)
     LUT4_D:I0->O         21   0.738   3.575  CU/GR_ADDRESS<1>1 (GR_address<1>)
     MUXF5:S->O            3   0.820   1.628  GR/GR_address<1>_rn_21 (GR/MUX_BLOCK_GR_address<1>_MUXF53)
     LUT4_L:I3->LO         1   0.738   0.000  ALU/ALU__AUX_7<1>lut (ALU/N7)
     MUXCY:S->O            1   0.842   0.000  ALU/ALU__AUX_7<1>cy (ALU/ALU__AUX_7<1>_cyo)
     MUXCY:CI->O           1   0.057   0.000  ALU/ALU__AUX_7<2>cy (ALU/ALU__AUX_7<2>_cyo)
     MUXCY:CI->O           1   0.057   0.000  ALU/ALU__AUX_7<3>cy (ALU/ALU__AUX_7<3>_cyo)
     MUXCY:CI->O           1   0.057   0.000  ALU/ALU__AUX_7<4>cy (ALU/ALU__AUX_7<4>_cyo)
     MUXCY:CI->O           1   0.057   0.000  ALU/ALU__AUX_7<5>cy (ALU/ALU__AUX_7<5>_cyo)
     MUXCY:CI->O           1   0.057   0.000  ALU/ALU__AUX_7<6>cy (ALU/ALU__AUX_7<6>_cyo)
     XORCY:CI->O           1   0.538   1.265  ALU/ALU__AUX_7<7>_xor (ALU/_AUX_7<7>)
     LUT4_L:I1->LO         1   0.738   0.100  ALU/ALU_out<7>50_SW0 (N1634)
     LUT4:I1->O            2   0.738   1.474  ALU/ALU_out<7>50 (ALU_out<7>)
     LUT4_L:I1->LO         1   0.738   0.000  DB_sel<0>31 (MUX_BLOCK_N48)
     MUXF5:I0->O           1   0.562   0.000  DB_sel<1>_rn_14 (MUX_BLOCK_DB_sel<1>_MUXF515)
     MUXF6:I0->O           2   0.412   1.474  DB_sel<2>_rn_6 (MUX_BLOCK_DB_sel<2>_MUXF67)
     LUT4_D:I3->O         14   0.738   2.860  DB_sel<3>71 (data_bus<7>)
     IOBUF:I->IO               5.652          data_7_IOBUF (data<7>)
    ----------------------------------------
    Total                     38.248ns (17.863ns logic, 20.385ns route)
                                       (46.7% logic, 53.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CU/DIVLE2:O'
  Total number of paths / destination ports: 32 / 8
-------------------------------------------------------------------------
Offset:              17.705ns (Levels of Logic = 7)
  Source:            DIV/q_out_4 (LATCH)
  Destination:       data<4> (PAD)
  Source Clock:      CU/DIVLE2:O falling

  Data Path: DIV/q_out_4 to data<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               2   1.509   1.474  DIV/q_out_4 (DIV/q_out_4)
     LUT4:I1->O            1   0.738   0.000  DIV_sel<1>_rn_3_F (N1846)
     MUXF5:I0->O           1   0.562   1.265  DIV_sel<1>_rn_3 (MUX_BLOCK_DIV_sel<1>_MUXF54)
     LUT3_L:I2->LO         1   0.738   0.000  DB_sel<0>18 (MUX_BLOCK_N29)
     MUXF5:I1->O           1   0.173   0.000  DB_sel<1>_rn_8 (MUX_BLOCK_DB_sel<1>_MUXF59)
     MUXF6:I0->O           2   0.412   1.474  DB_sel<2>_rn_3 (MUX_BLOCK_DB_sel<2>_MUXF64)
     LUT4_D:I3->O         15   0.738   2.970  DB_sel<3>41 (data_bus<4>)
     IOBUF:I->IO               5.652          data_4_IOBUF (data<4>)
    ----------------------------------------
    Total                     17.705ns (10.522ns logic, 7.183ns route)
                                       (59.4% logic, 40.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CU/MULLE2:O'
  Total number of paths / destination ports: 16 / 8
-------------------------------------------------------------------------
Offset:              16.934ns (Levels of Logic = 6)
  Source:            MUL/mul_out_4 (LATCH)
  Destination:       data<4> (PAD)
  Source Clock:      CU/MULLE2:O falling

  Data Path: MUL/mul_out_4 to data<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   1.509   1.265  MUL/mul_out_4 (MUL/mul_out_4)
     LUT3:I1->O            1   0.738   1.265  MUX_2_MUL/mux2_out<4>1 (MUL_sel_out<4>)
     LUT3_L:I1->LO         1   0.738   0.000  DB_sel<0>18 (MUX_BLOCK_N29)
     MUXF5:I1->O           1   0.173   0.000  DB_sel<1>_rn_8 (MUX_BLOCK_DB_sel<1>_MUXF59)
     MUXF6:I0->O           2   0.412   1.474  DB_sel<2>_rn_3 (MUX_BLOCK_DB_sel<2>_MUXF64)
     LUT4_D:I3->O         15   0.738   2.970  DB_sel<3>41 (data_bus<4>)
     IOBUF:I->IO               5.652          data_4_IOBUF (data<4>)
    ----------------------------------------
    Total                     16.934ns (9.960ns logic, 6.974ns route)
                                       (58.8% logic, 41.2% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Delay:               14.695ns (Levels of Logic = 6)
  Source:            data<4> (PAD)
  Destination:       data<4> (PAD)

  Data Path: data<4> to data<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O           1   0.989   1.265  data_4_IOBUF (N1552)
     LUT3_L:I2->LO         1   0.738   0.000  DB_sel<0>17 (MUX_BLOCK_N26)
     MUXF5:I0->O           1   0.562   0.000  DB_sel<1>_rn_7 (MUX_BLOCK_DB_sel<1>_MUXF58)
     MUXF6:I1->O           2   0.307   1.474  DB_sel<2>_rn_3 (MUX_BLOCK_DB_sel<2>_MUXF64)
     LUT4_D:I3->O         15   0.738   2.970  DB_sel<3>41 (data_bus<4>)
     IOBUF:I->IO               5.652          data_4_IOBUF (data<4>)
    ----------------------------------------
    Total                     14.695ns (8.986ns logic, 5.709ns route)
                                       (61.2% logic, 38.8% route)

=========================================================================
CPU : 14.27 / 14.45 s | Elapsed : 14.00 / 14.00 s
 
--> 

Total memory usage is 94952 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   46 (   0 filtered)
Number of infos    :    1 (   0 filtered)