cpu.syr

cup 的设计源代码

WARNING:Xst:646 - Signal <s9<8>> is assigned but never used.
WARNING:Xst:737 - Found 8-bit latch for signal <r_out>.
WARNING:Xst:737 - Found 16-bit latch for signal <q_out>.
    Found 8-bit adder for signal <$n0001> created at line 37.
    Summary:
	inferred   1 Adder/Subtractor(s).
Unit <DIV> synthesized.


Synthesizing Unit <MUL>.
    Related source file is "MUL.v".
WARNING:Xst:737 - Found 16-bit latch for signal <mul_out>.
    Found 16-bit adder for signal <$n0001> created at line 30.
    Found 16-bit adder for signal <$n0002>.
    Found 16-bit adder for signal <$n0003>.
    Found 16-bit adder for signal <$n0004>.
    Found 16-bit adder for signal <$n0005>.
    Found 16-bit adder for signal <$n0006>.
    Found 16-bit adder for signal <$n0007>.
    Summary:
	inferred   7 Adder/Subtractor(s).
Unit <MUL> synthesized.


Synthesizing Unit <ALU>.
    Related source file is "ALU.v".
    Found 9-bit subtractor for signal <$AUX_7>.
    Found 8-bit adder carry out for signal <$n0001>.
    Found 8-bit adder carry out for signal <$n0002>.
    Summary:
	inferred   3 Adder/Subtractor(s).
Unit <ALU> synthesized.


Synthesizing Unit <GR>.
    Related source file is "GR.v".
    Found 8-bit 8-to-1 multiplexer for signal <GR_out>.
    Found 64-bit register for signal <register>.
    Summary:
	inferred  64 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
Unit <GR> synthesized.


Synthesizing Unit <SP>.
    Related source file is "SP.v".
    Found 8-bit updown counter for signal <SP_out>.
    Summary:
	inferred   1 Counter(s).
Unit <SP> synthesized.


Synthesizing Unit <PC>.
    Related source file is "PC.v".
    Found 8-bit up counter for signal <PC_out>.
    Summary:
	inferred   1 Counter(s).
Unit <PC> synthesized.


Synthesizing Unit <mux16>.
    Related source file is "mux16.v".
    Found 8-bit 16-to-1 multiplexer for signal <mux16_out>.
    Summary:
	inferred   8 Multiplexer(s).
Unit <mux16> synthesized.


Synthesizing Unit <mux4>.
    Related source file is "mux4.v".
    Found 8-bit 4-to-1 multiplexer for signal <mux4_out>.
    Summary:
	inferred   8 Multiplexer(s).
Unit <mux4> synthesized.


Synthesizing Unit <mux2>.
    Related source file is "mux2.v".
Unit <mux2> synthesized.


Synthesizing Unit <register>.
    Related source file is "register.v".
    Found 8-bit register for signal <reg_out>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <register> synthesized.


Synthesizing Unit <CPU>.
    Related source file is "CPU.v".
    Found 8-bit tristate buffer for signal <data>.
    Summary:
	inferred   8 Tristate(s).
Unit <CPU> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:6]> with speed1 encoding.
-------------------
 State | Encoding
-------------------
 000   | 001000
 001   | 010000
 010   | 000100
 011   | 000001
 100   | 000010
 101   | 100000
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 11
 16-bit adder                      : 7
 8-bit adder                       : 1
 8-bit adder carry out             : 2
 9-bit subtractor                  : 1
# Counters                         : 2
 8-bit up counter                  : 1
 8-bit updown counter              : 1
# Registers                        : 19
 1-bit register                    : 5
 8-bit register                    : 14
# Latches                          : 3
 16-bit latch                      : 2
 8-bit latch                       : 1
# Multiplexers                     : 9
 1-bit 4-to-1 multiplexer          : 3
 2-bit 4-to-1 multiplexer          : 1
 8-bit 16-to-1 multiplexer         : 1
 8-bit 4-to-1 multiplexer          : 3
 8-bit 8-to-1 multiplexer          : 1
# Tristates                        : 1
 8-bit tristate buffer             : 1
# Xors                             : 144
 1-bit xor3                        : 144

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <reg_out_7> is unconnected in block <C>.
WARNING:Xst:1291 - FF/Latch <reg_out_1> is unconnected in block <C>.
WARNING:Xst:1291 - FF/Latch <reg_out_2> is unconnected in block <C>.
WARNING:Xst:1291 - FF/Latch <reg_out_3> is unconnected in block <C>.
WARNING:Xst:1291 - FF/Latch <reg_out_4> is unconnected in block <C>.
WARNING:Xst:1291 - FF/Latch <reg_out_5> is unconnected in block <C>.
WARNING:Xst:1291 - FF/Latch <reg_out_6> is unconnected in block <C>.
WARNING:Xst:1291 - FF/Latch <reg_out_7> is unconnected in block <Z>.
WARNING:Xst:1291 - FF/Latch <reg_out_1> is unconnected in block <Z>.
WARNING:Xst:1291 - FF/Latch <reg_out_2> is unconnected in block <Z>.
WARNING:Xst:1291 - FF/Latch <reg_out_3> is unconnected in block <Z>.
WARNING:Xst:1291 - FF/Latch <reg_out_4> is unconnected in block <Z>.
WARNING:Xst:1291 - FF/Latch <reg_out_5> is unconnected in block <Z>.
WARNING:Xst:1291 - FF/Latch <reg_out_6> is unconnected in block <Z>.
Register <C/reg_out_4> equivalent to <C/reg_out_3> has been removed
Register <C/reg_out_5> equivalent to <C/reg_out_3> has been removed
Register <C/reg_out_6> equivalent to <C/reg_out_3> has been removed
Register <C/reg_out_2> equivalent to <C/reg_out_1> has been removed
Register <C/reg_out_3> equivalent to <C/reg_out_1> has been removed
Register <Z/reg_out_1> equivalent to <Z/reg_out_7> has been removed
Register <Z/reg_out_2> equivalent to <Z/reg_out_7> has been removed
Register <Z/reg_out_6> equivalent to <Z/reg_out_7> has been removed
Register <Z/reg_out_5> equivalent to <Z/reg_out_7> has been removed
Register <Z/reg_out_4> equivalent to <Z/reg_out_7> has been removed
Register <Z/reg_out_3> equivalent to <Z/reg_out_7> has been removed
Register <C/reg_out_1> equivalent to <C/reg_out_7> has been removed
WARNING:Xst:1291 - FF/Latch <C/reg_out_7> is unconnected in block <CPU>.
WARNING:Xst:1291 - FF/Latch <Z/reg_out_7> is unconnected in block <CPU>.

Optimizing unit <CPU> ...

Optimizing unit <DIV_CAS> ...

Optimizing unit <mux2> ...

Optimizing unit <DIV> ...

Optimizing unit <CU> ...

Optimizing unit <MUL> ...

Optimizing unit <ALU> ...

Optimizing unit <GR> ...
Loading device for application Rf_Device from file 'v100.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block CPU, actual ratio is 37.
FlipFlop CU/state_FFd2 has been replicated 1 time(s)
FlipFlop CU/state_FFd4 has been replicated 2 time(s)
FlipFlop CU/state_FFd5 has been replicated 2 time(s)
FlipFlop IR/reg_out_3 has been replicated 2 time(s)
FlipFlop IR/reg_out_4 has been replicated 3 time(s)
FlipFlop IR/reg_out_5 has been replicated 2 time(s)
FlipFlop IR/reg_out_6 has been replicated 1 time(s)
FlipFlop IR/reg_out_7 has been replicated 2 time(s)
PACKER Warning: Lut DIV/DIV__n0001<1>lut driving carry DIV/DIV__n0001<1>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0002<8>lut driving carry MUL/MUL__n0002<8>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0002<9>lut driving carry MUL/MUL__n0002<9>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0002<10>lut driving carry MUL/MUL__n0002<10>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0002<11>lut driving carry MUL/MUL__n0002<11>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0002<12>lut driving carry MUL/MUL__n0002<12>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0002<13>lut driving carry MUL/MUL__n0002<13>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0003<6>lut driving carry MUL/MUL__n0003<6>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0003<7>lut driving carry MUL/MUL__n0003<7>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0003<8>lut driving carry MUL/MUL__n0003<8>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0003<9>lut driving carry MUL/MUL__n0003<9>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0003<10>lut driving carry MUL/MUL__n0003<10>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0003<11>lut driving carry MUL/MUL__n0003<11>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0005<4>lut driving carry MUL/MUL__n0005<4>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0005<5>lut driving carry MUL/MUL__n0005<5>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0005<6>lut driving carry MUL/MUL__n0005<6>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0005<7>lut driving carry MUL/MUL__n0005<7>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0005<8>lut driving carry MUL/MUL__n0005<8>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0005<9>lut driving carry MUL/MUL__n0005<9>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0006<2>lut driving carry MUL/MUL__n0006<2>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0006<3>lut driving carry MUL/MUL__n0006<3>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0006<4>lut driving carry MUL/MUL__n0006<4>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0006<5>lut driving carry MUL/MUL__n0006<5>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0006<6>lut driving carry MUL/MUL__n0006<6>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0006<7>lut driving carry MUL/MUL__n0006<7>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0004<7>lut driving carry MUL/MUL__n0004<7>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0007<3>lut driving carry MUL/MUL__n0007<3>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0001<5>lut driving carry MUL/MUL__n0001<5>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.
PACKER Warning: Lut MUL/MUL__n0001<6>lut driving carry MUL/MUL__n0001<6>cy can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : CPU.ngr
Top Level Output File Name         : CPU
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 21

Macro Statistics :
# Registers                        : 15
#      8-bit register              : 15
# Counters                         : 1
#      8-bit up counter            : 1
# Multiplexers                     : 9
#      1-bit 4-to-1 multiplexer    : 3
#      2-bit 4-to-1 multiplexer    : 1
#      8-bit 16-to-1 multiplexer   : 1
#      8-bit 4-to-1 multiplexer    : 3
#      8-bit 8-to-1 multiplexer    : 1
# Tristates                        : 1
#      8-bit tristate buffer       : 1
# Adders/Subtractors               : 12
#      16-bit adder                : 7
#      8-bit adder                 : 1
#      8-bit adder carry out       : 2
#      8-bit addsub                : 1
#      9-bit subtractor            : 1
# Xors                             : 144
#      1-bit xor3                  : 144