cpu.syr

cup 的设计源代码

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.17 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
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--> Reading design: CPU.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "CPU.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "CPU"
Output Format                      : NGC
Target Device                      : xcv100-4-pq240

---- Source Options
Top Module Name                    : CPU
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : CPU.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "register.v"
Module <register> compiled
Compiling verilog file "mux2.v"
Module <mux2> compiled
Compiling verilog file "mux4.v"
Module <mux4> compiled
Compiling verilog file "mux16.v"
Module <mux16> compiled
Compiling verilog file "PC.v"
Module <PC> compiled
Compiling verilog file "SP.v"
Module <SP> compiled
Compiling verilog file "GR.v"
Module <GR> compiled
Compiling verilog file "ALU.v"
Module <ALU> compiled
Compiling verilog file "MUL.v"
Module <MUL> compiled
Compiling verilog file "DIV_CAS.v"
Module <DIV_CAS> compiled
Compiling verilog file "DIV_row.v"
Module <DIV_row> compiled
Compiling verilog file "DIV.v"
Module <DIV> compiled
Compiling verilog file "CU.v"
Module <CU> compiled
Compiling verilog file "CPU.v"
Module <CPU> compiled
No errors in compilation
Analysis of file <"CPU.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
WARNING:HDLCompilers:259 - "CPU.v" line 86 Connection to input port 'reg_in' does not match port size
WARNING:HDLCompilers:261 - "CPU.v" line 86 Connection to output port 'reg_out' does not match port size
WARNING:HDLCompilers:259 - "CPU.v" line 87 Connection to input port 'reg_in' does not match port size
WARNING:HDLCompilers:261 - "CPU.v" line 87 Connection to output port 'reg_out' does not match port size
WARNING:HDLCompilers:259 - "CPU.v" line 95 Connection to input port 'm0_in' does not match port size
WARNING:HDLCompilers:259 - "CPU.v" line 95 Connection to input port 'm1_in' does not match port size
WARNING:HDLCompilers:259 - "CPU.v" line 95 Connection to input port 'm2_in' does not match port size
WARNING:HDLCompilers:259 - "CPU.v" line 95 Connection to input port 'm3_in' does not match port size
WARNING:HDLCompilers:261 - "CPU.v" line 95 Connection to output port 'mux4_out' does not match port size
Analyzing top module <CPU>.
	width = 8
Module <CPU> is correct for synthesis.
 
Analyzing module <register>.
	width = 8
Module <register> is correct for synthesis.
 
Analyzing module <mux2>.
	width = 8
Module <mux2> is correct for synthesis.
 
Analyzing module <mux4>.
	width = 8
Module <mux4> is correct for synthesis.
 
Analyzing module <mux16>.
	width = 8
Module <mux16> is correct for synthesis.
 
Analyzing module <PC>.
	width = 8
Module <PC> is correct for synthesis.
 
Analyzing module <SP>.
	width = 8
Module <SP> is correct for synthesis.
 
Analyzing module <GR>.
	width = 8
Module <GR> is correct for synthesis.
 
Analyzing module <ALU>.
	width = 8
	width_op = 5
	ADD = <u>00000000000000000000000000000100
	SUB = <u>00000000000000000000000000000101
	SHL = <u>00000000000000000000000000001011
	SHCL = <u>00000000000000000000000000001100
	SHR = <u>00000000000000000000000000001001
	SHCR = <u>00000000000000000000000000001010
	INC = <u>00000000000000000000000000001101
	REV = <u>00000000000000000000000000001110
Module <ALU> is correct for synthesis.
 
Analyzing module <MUL>.
	width = 8
Module <MUL> is correct for synthesis.
 
Analyzing module <DIV>.
	width_a = 16
	width_b = 8
Module <DIV> is correct for synthesis.
 
Analyzing module <DIV_row>.
	width = 8
Module <DIV_row> is correct for synthesis.
 
Analyzing module <DIV_CAS>.
WARNING:Xst:905 - "DIV_CAS.v" line 35: The signals <b> are missing in the sensitivity list of always block.
Module <DIV_CAS> is correct for synthesis.
 
Analyzing module <CU>.
	FIRST = <u>00000000000000000000000000000000
	SECOND = <u>00000000000000000000000000000001
	THIRD = <u>00000000000000000000000000000010
	HALT = <u>00000000000000000000000000000011
	FORTH = <u>00000000000000000000000000000100
	FIFTH = <u>00000000000000000000000000000101
	SP_START = <u>00000000000000000000000011111111
Module <CU> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <CLE> in unit <CU> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <DIV_CAS>.
    Related source file is "DIV_CAS.v".
WARNING:Xst:646 - Signal <b> is assigned but never used.
    Found 1-bit xor3 for signal <s_out>.
    Summary:
	inferred   1 Xor(s).
Unit <DIV_CAS> synthesized.


Synthesizing Unit <DIV_row>.
    Related source file is "DIV_row.v".
Unit <DIV_row> synthesized.


Synthesizing Unit <CU>.
    Related source file is "CU.v".
WARNING:Xst:647 - Input <AR_OUT<7:3>> is never used.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 7                                              |
    | Inputs             | 1                                              |
    | Outputs            | 5                                              |
    | Clock              | CLK (rising_edge)                              |
    | Reset              | RST (negative)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | 101                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit 4-to-1 multiplexer for signal <SPDE>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
    Found 2-bit 4-to-1 multiplexer for signal <$old_AB_SEL_22>.
    Found 1-bit 4-to-1 multiplexer for signal <$old_ARLE_23>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   5 Multiplexer(s).
Unit <CU> synthesized.


Synthesizing Unit <DIV>.
    Related source file is "DIV.v".
WARNING:Xst:646 - Signal <s10<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s11<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s12<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s13<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s14<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s15<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s1<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s2<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s3<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s4<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s5<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s6<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s7<8>> is assigned but never used.
WARNING:Xst:646 - Signal <s8<8>> is assigned but never used.