div_row.v

来自「cup 的设计源代码」· Verilog 代码 · 共 47 行

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    19:05:12 10/11/08
// Design Name:    
// Module Name:    DIV_row
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module DIV_row(a_in, b_in, p_in, b_out, s_out, q_out);
    parameter width=8;

    input[width:0] a_in;
    input[width:0] b_in;
    input p_in;
    output[width:0] b_out;
    output[width:0] s_out;
    output q_out;
    
    wire p1,p2,p3,p4,p5,p6,p7,p8;
    wire c1,c2,c3,c4,c5,c6,c7,c8;
    wire p_c;
    
    DIV_CAS CAS8 (.a_in(a_in[width]), .b_in(b_in[width]), .c_in(c8), .p_in(p_in), .s_out(s_out[width]), .b_out(b_out[width]), .c_out(q_out), .p_out(p8));
    DIV_CAS CAS7 (.a_in(a_in[width-1]), .b_in(b_in[width-1]), .c_in(c7), .p_in(p8), .s_out(s_out[width-1]), .b_out(b_out[width-1]), .c_out(c8), .p_out(p7));
    DIV_CAS CAS6 (.a_in(a_in[width-2]), .b_in(b_in[width-2]), .c_in(c6), .p_in(p7), .s_out(s_out[width-2]), .b_out(b_out[width-2]), .c_out(c7), .p_out(p6));
    DIV_CAS CAS5 (.a_in(a_in[width-3]), .b_in(b_in[width-3]), .c_in(c5), .p_in(p6), .s_out(s_out[width-3]), .b_out(b_out[width-3]), .c_out(c6), .p_out(p5));
    DIV_CAS CAS4 (.a_in(a_in[width-4]), .b_in(b_in[width-4]), .c_in(c4), .p_in(p5), .s_out(s_out[width-4]), .b_out(b_out[width-4]), .c_out(c5), .p_out(p4));
    DIV_CAS CAS3 (.a_in(a_in[width-5]), .b_in(b_in[width-5]), .c_in(c3), .p_in(p4), .s_out(s_out[width-5]), .b_out(b_out[width-5]), .c_out(c4), .p_out(p3));
    DIV_CAS CAS2 (.a_in(a_in[width-6]), .b_in(b_in[width-6]), .c_in(c2), .p_in(p3), .s_out(s_out[width-6]), .b_out(b_out[width-6]), .c_out(c3), .p_out(p2));
    DIV_CAS CAS1 (.a_in(a_in[width-7]), .b_in(b_in[width-7]), .c_in(c1), .p_in(p2), .s_out(s_out[width-7]), .b_out(b_out[width-7]), .c_out(c2), .p_out(p1));
    DIV_CAS CAS0 (.a_in(a_in[width-8]), .b_in(b_in[width-8]), .c_in(p_c), .p_in(p1), .s_out(s_out[width-8]), .b_out(b_out[width-8]), .c_out(c1), .p_out(p_c));


endmodule