alu.v

cup 的设计源代码

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    20:02:50 10/08/08
// Design Name:    
// Module Name:    ALU
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module ALU(AC_in, C_in, GR_in, op_in, ALU_out, C_out, Z_out);
    parameter width=8;
    parameter width_op=5;
    parameter ADD='b00100;
    parameter SUB='b00101;
    parameter SHL='b01011;
	 parameter SHCL='b01100;
    parameter SHR='b01001;
	 parameter SHCR='b01010;
    parameter INC='b01101;
    parameter REV='b01110;

    input[width-1:0] AC_in;
    input C_in;
    input[width-1:0] GR_in;
    input[width_op-1:0] op_in;
    output[width-1:0] ALU_out;
    output C_out;
    output Z_out;

    reg[width-1:0] ALU_out;
    reg C_out;
    
   
    assign Z_out=(ALU_out=='b0)?'b1:'b0;
    
    always@(AC_in or C_in or GR_in or op_in)
    begin
        case(op_in)
        ADD:begin {C_out,ALU_out}=AC_in+GR_in;end
        SUB:begin {C_out,ALU_out}=AC_in-GR_in;end
        SHL:begin {C_out,ALU_out}={AC_in[width-2:0],1'b0};end
        SHCL:begin {C_out,ALU_out}={AC_in,C_in};end
        SHR:begin {C_out,ALU_out}={1'b0,AC_in[width-1:1]};end
        SHCR:begin {C_out,ALU_out}={AC_in[0],C_in,AC_in[width-1:1]};end
        REV:begin {C_out,ALU_out}={1'b0,~AC_in};end
        INC:begin {C_out,ALU_out}=AC_in+'b1;end
        default:begin {C_out,ALU_out}={C_in,8'b0};end  		
        endcase
    end	  
endmodule